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Freescale Semiconductor, Inc.
MC68HC908JG16
Freescale Semiconductor, Inc...
Technical Data
M68HC08
Microcontrollers
MC68HC908JG16/D Rev. 1, 5/2002
WWW.MOTOROLA.COM/SEMICONDUCTORS
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC68HC908JG16
Freescale Semiconductor, Inc...
Technical Data
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and the Stylized M logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc.
(c) Motorola, Inc., 2002
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Technical Data
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
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Revision History
Date May 2002 Revision Level 1 First general release. Description Page Number(s) --
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MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Technical Data -- MC68HC908JG16
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . 29 Section 2. Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Section 3. Random-Access Memory (RAM) . . . . . . . . . . . . . 55 Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Section 5. Configuration Register (CONFIG) . . . . . . . . . . . . 69 Section 6. Central Processor Unit (CPU). . . . . . . . . . . . . . . . 73 Section 7. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Section 8. System Integration Module (SIM) . . . . . . . . . . . . . 95 Section 9. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . 121 Section 10. Timer Interface Module (TIM) . . . . . . . . . . . . . . 135 Section 11. Universal Serial Bus Module (USB) . . . . . . . . . 159 Section 12. Serial Communications Interface Module (SCI). . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Section 13. Analog-to-Digital Converter (ADC) . . . . . . . . . 245 Section 14. Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . 255 Section 15. External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . 275 Section 16. Keyboard Interrupt Module (KBI) . . . . . . . . . . . 283 Section 17. Computer Operating Properly (COP) . . . . . . . . 291 Section 18. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . 297 Section 19. Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . 301 Section 20. Electrical Specifications . . . . . . . . . . . . . . . . . . 309 Section 21. Mechanical Specifications . . . . . . . . . . . . . . . . 319 Section 22. Ordering Information. . . . . . . . . . . . . . . . . . . . . 321
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List of Sections
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MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Technical Data -- MC68HC908JG16
Table of Contents
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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1.2 1.3 1.4 1.5
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6.1 Power Supply Pins (VDD, VSS) . . . . . . . . . . . . . . . . . . . . . . .33 1.6.2 Voltage Regulator Output Pin (VREG). . . . . . . . . . . . . . . . . . 34 1.6.3 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 35 1.6.4 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.5 External Interrupt Pins (IRQ, PTE4/D-) . . . . . . . . . . . . . . . .35 1.6.6 Analog Power Supply Pins (VDDA, VSSA) . . . . . . . . . . . . . . . 35 1.6.7 Analog Voltage Regulator Out (VREGA) . . . . . . . . . . . . . . . . 35 1.6.8 Port A Input/Output (I/O) Pins (PTA7/KBA7/AD7-PTA0/KBA0/AD0) . . . . . . . . . . . . . . . 36 1.6.9 Port B I/O Pins (PTB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.10 Port C I/O Pins (PTC1/RxD, PTC0/TxD) . . . . . . . . . . . . . . . 36 1.6.11 Port D I/O Pins (PTD3-PTD0) . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.12 Port E I/O Pins (PTE4/D-, PTE3/D+, PTE2/T2CH01, PTE1/T1CH01, PTE0/TCLK). . . . . . . . . . . . . . . . . . . . . . 36
Section 2. Memory Map
2.1 2.2 2.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 39
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2.4 2.5 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Section 3. Random-Access Memory (RAM)
3.1 3.2 3.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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Section 4. FLASH Memory
4.1 4.2 4.3 4.4 4.5 4.6 4.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 60 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 61 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.8 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.8.1 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . .64 4.9 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 4.9.1 Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.9.2 ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 4.9.3 PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.9.4 VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Section 5. Configuration Register (CONFIG)
5.1 5.2 5.3 5.4
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Table of Contents
Section 6. Central Processor Unit (CPU)
6.1 6.2 6.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .78 6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.7 6.8 6.9 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Section 7. Oscillator (OSC)
7.1 7.2 7.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . . 92
7.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . 93 7.4.2 Crystal Amplifier Output Pin (OSC1) . . . . . . . . . . . . . . . . . . 93 7.4.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . 93 7.4.4 Crystal Output Frequency Signal (OSCXCLK). . . . . . . . . . . 93 7.4.5 Clock Doubler Out (OSCDCLK) . . . . . . . . . . . . . . . . . . . . . . 93 7.4.6 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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7.5.2 7.6 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 94
Section 8. System Integration Module (SIM)
8.1 8.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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8.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 98 8.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . 99 8.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 99 8.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 99 8.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 101 8.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . 103 8.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . 104 8.4.2.6 Universal Serial Bus (USB) Reset . . . . . . . . . . . . . . . . . 104 8.4.2.7 Registers Values After Different Resets. . . . . . . . . . . . . 104 8.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 105 8.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 106 8.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .106 8.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 110 8.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 8.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 113
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8.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 8.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.8.1 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . 117 8.8.2 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . 118 8.8.3 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . .119
Section 9. Monitor ROM (MON)
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9.1 9.2 9.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 9.4.3 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 9.4.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.5.1 Extended Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Section 10. Timer Interface Module (TIM)
10.1 10.2 10.3 10.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 142 10.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 143
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10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 143 10.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 144 10.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 145 10.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 10.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
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10.8
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.9.1 TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . . 149 10.9.2 TIM Channel I/O Pins (PTE1/T1CH01:PTE2/T2CH01) . . . 149 10.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 150 10.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 153 10.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . .154 10.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Section 11. Universal Serial Bus Module (USB)
11.1 11.2 11.3 11.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11.5.1 USB Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.5.1.1 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 11.5.1.2 Packet Identifier Field . . . . . . . . . . . . . . . . . . . . . . . . . .169 11.5.1.3 Address Field (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . .170 11.5.1.4 Endpoint Field (ENDP). . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.5.1.5 Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . 170 11.5.1.6 End-of-Packet (EOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.5.2 Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
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11.5.3 Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.5.4 Resume After Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.5.4.1 Host Initiated Resume . . . . . . . . . . . . . . . . . . . . . . . . . .173 11.5.4.2 USB Reset Signalling. . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.5.4.3 Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.5.5 Low-Speed Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.6 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Freescale Semiconductor, Inc...
11.7 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7.1 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7.2 USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7.2.1 Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . 176 11.7.2.2 Low Speed (1.5 Mbps) Driver Characteristics . . . . . . . . 176 11.7.2.3 Receiver Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.2.4 Data Source Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.2.5 Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . .178 11.7.3 USB Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.8.1 USB Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.8.2 USB Interrupt Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . .181 11.8.3 USB Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .183 11.8.4 USB Interrupt Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .186 11.8.5 USB Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.8.6 USB Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.8.7 USB Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.8.8 USB Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.8.9 USB Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.8.10 USB Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.8.11 USB Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.8.12 USB Endpoint 0 Data Registers . . . . . . . . . . . . . . . . . . . . . 196 11.8.13 USB Endpoint 1 Data Registers . . . . . . . . . . . . . . . . . . . . . 197 11.8.14 USB Endpoint 2 Data Registers . . . . . . . . . . . . . . . . . . . . . 198 11.9 USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.9.1 USB End-of-Transaction Interrupt . . . . . . . . . . . . . . . . . . .199 11.9.1.1 Receive Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . .200 11.9.1.2 Transmit Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . 202 11.9.1.3 Transmit Endpoint 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com Technical Data 13
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11.9.1.4 Transmit Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.9.1.5 Receive Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.9.2 Resume Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.9.3 End-of-Packet Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Section 12. Serial Communications Interface Module (SCI)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Freescale Semiconductor, Inc...
12.2 12.3 12.4
12.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 12.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 12.5.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.5.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.5.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.5.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.5.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . . 215 12.5.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 215 12.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12.5.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 12.5.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 12.5.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12.5.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 12.5.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 12.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.7 12.8
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SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . . 226 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
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12.8.1 12.8.2
TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Freescale Semiconductor, Inc...
12.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 12.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 12.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 12.9.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 12.9.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 12.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 12.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Section 13. Analog-to-Digital Converter (ADC)
13.1 13.2 13.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 13.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 13.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.7.1 ADC Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . 250 13.7.2 ADC Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . 250 13.7.3 ADC Voltage Reference High Pin (VREFH). . . . . . . . . . . . . 250 13.7.4 ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . 250 13.7.5 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 251
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com
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13.8.2 13.8.3 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 253
Section 14. Input/Output (I/O) Ports
14.1 14.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Freescale Semiconductor, Inc...
14.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 14.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 14.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . 259 14.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 14.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 14.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . 261 14.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14.5.2 Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . 264 14.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 14.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . 267 14.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.7.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . . 271 14.8 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 14.8.1 Port Option Control Register . . . . . . . . . . . . . . . . . . . . . . . 273
Section 15. External Interrupt (IRQ)
15.1 15.2 15.3 15.4 15.5 15.6
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 PTE4/D- Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
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15.7 15.8 15.9
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .279 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 280 IRQ Option Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . 281
Section 16. Keyboard Interrupt Module (KBI)
16.1 16.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Freescale Semiconductor, Inc...
16.3 16.4 16.5 16.6
16.7 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16.7.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 288 16.7.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 289 16.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 16.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.9 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .290
Section 17. Computer Operating Properly (COP)
17.1 17.2 17.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
17.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.1 OSCDCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 17.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
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17.4.7 17.4.8 17.5 17.6 17.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 294 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Freescale Semiconductor, Inc...
17.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 17.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 17.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 17.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .296
Section 18. Low-Voltage Inhibit (LVI)
18.1 18.2 18.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 18.4.1 Low VDD Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 18.4.2 Low VREG Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 18.5 LVI Control and Configuration . . . . . . . . . . . . . . . . . . . . . . . . 299
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Section 19. Break Module (BRK)
19.1 19.2 19.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 19.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . .304 19.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 304 19.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 304 19.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 304
Technical Data 18 Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Table of Contents
19.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 19.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 19.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 19.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 19.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . 305 19.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .306 19.6.3 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 308
Freescale Semiconductor, Inc...
Section 20. Electrical Specifications
20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 20.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .310 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 311 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 312 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 314
20.10 USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 314 20.11 USB Low-Speed Source Electrical Characteristics . . . . . . . . 315 20.12 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 20.13 ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 317 20.14 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . 318
Section 21. Mechanical Specifications
21.1 21.2 21.3
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 32-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . 320
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Table of Contents Section 22. Ordering Information
22.1 22.2 22.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Freescale Semiconductor, Inc...
Technical Data 20 Table of Contents For More Information On This Product, Go to: www.freescale.com
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Technical Data -- MC68HC908JG16
List of Figures
Figure 1-1 1-2 1-3 1-4 2-1 2-2 4-1 4-2 4-3 4-4 4-5 5-1 6-1 6-2 6-3 6-4 6-5 6-6 7-1 8-1 8-2 8-3 8-4 8-5
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Title
Page
Freescale Semiconductor, Inc...
MC68HC908JG16 MCU Block Diagram. . . . . . . . . . . . . . . . . . 32 32-Pin LQFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Regulator Supply Capacitor Configuration . . . . . . . . . . . . . . . .34 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . . 42 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 58 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . . 59 FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . 63 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . . 64 FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . . . 64 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . .70 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . 78 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . . 92 SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 SIM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Technical Data List of Figures For More Information On This Product, Go to: www.freescale.com 21
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List of Figures
Figure 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 Title Page
Freescale Semiconductor, Inc...
Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 109 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .110 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . .112 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . .112 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . 115 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . 115 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . 116 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . 117 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . 118 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . 119 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . . 125 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . .132 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 133 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 144 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 150 TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . . . . 152 TIM Counter Registers Low (TCNTL) . . . . . . . . . . . . . . . . . . . 153 TIM Counter Modulo Register High (TMODH) . . . . . . . . . . . .153 TIM Counter Modulo Register Low (TMODL) . . . . . . . . . . . . . 153 TIM Channel 0 Status and Control Register (TSC0) . . . . . . . 154
Technical Data 22 List of Figures For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
List of Figures
Figure 10-10 10-11 10-12 10-13 10-14 10-15 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 11-27 11-28 11-29
Title
Page
TIM Channel 1 Status and Control Register (TSC1) . . . . . . . 154 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . . . 158 TIM Channel 0 Register Low (TCH0L) . . . . . . . . . . . . . . . . . . 158 TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . . . 158 TIM Channel 1 Register Low (TCH1L) . . . . . . . . . . . . . . . . . . 158 USB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .162 USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Supported Transaction Types Per Endpoint. . . . . . . . . . . . . . 167 Supported USB Packet Types . . . . . . . . . . . . . . . . . . . . . . . . 168 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 SOP, Sync Signaling, and Voltage Levels . . . . . . . . . . . . . . . 169 EOP Transaction Voltage Levels . . . . . . . . . . . . . . . . . . . . . . 171 EOP Width Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 External Low-Speed Device Configuration . . . . . . . . . . . . . . .174 Regulator Electrical Connections . . . . . . . . . . . . . . . . . . . . . . 175 Receiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 Differential Input Sensitivity Range. . . . . . . . . . . . . . . . . . . . . 177 Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . 178 USB Address Register (UADDR) . . . . . . . . . . . . . . . . . . . . . . 180 USB Interrupt Register 0 (UIR0) . . . . . . . . . . . . . . . . . . . . . . . 181 USB Interrupt Register 1 (UIR1) . . . . . . . . . . . . . . . . . . . . . . . 183 USB Interrupt Register 2 (UIR2) . . . . . . . . . . . . . . . . . . . . . . . 186 USB Control Register 0 (UCR0) . . . . . . . . . . . . . . . . . . . . . . . 187 USB Control Register 1 (UCR1) . . . . . . . . . . . . . . . . . . . . . . . 188 USB Control Register 2 (UCR2) . . . . . . . . . . . . . . . . . . . . . . . 189 USB Control Register 3 (UCR3) . . . . . . . . . . . . . . . . . . . . . . . 191 USB Control Register 4 (UCR4) . . . . . . . . . . . . . . . . . . . . . . . 193 USB Status Register 0 (USR0). . . . . . . . . . . . . . . . . . . . . . . . 194 USB Status Register 2 (USR1). . . . . . . . . . . . . . . . . . . . . . . . 195 USB Endpoint 0 Data Registers (UE0D0-UE0D7). . . . . . . . . 196 USB Endpoint 1 Data Registers (UE1D0-UE1D7). . . . . . . . . 197 USB Endpoint 2 Data Registers (UE2D0-UE2D7). . . . . . . . . 198 OUT Token Data Flow for Receive Endpoint 0. . . . . . . . . . . . 200
Freescale Semiconductor, Inc...
MC68HC908JG16 -- Rev. 1.0 MOTOROLA List of Figures For More Information On This Product, Go to: www.freescale.com
Technical Data 23
Freescale Semiconductor, Inc.
List of Figures
Figure Title Page
11-30 SETUP Token Data Flow for Receive Endpoint 0 . . . . . . . . . 201 11-31 IN Token Data Flow for Transmit Endpoint 0 . . . . . . . . . . . . . 202 11-32 IN Token Data Flow for Transmit Endpoint 1 . . . . . . . . . . . . . 203 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 13-1 13-2 13-3 13-4 13-5 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 SCI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 209 SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 217 Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . . 228 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . . 231 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . . 233 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . . 236 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . . 240 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . . 242 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .246 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . 251 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .253 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .258 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 259 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .261 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 261 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .263 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . 264
Freescale Semiconductor, Inc...
Technical Data 24
MC68HC908JG16 -- Rev. 1.0 List of Figures For More Information On This Product, Go to: www.freescale.com MOTOROLA
Freescale Semiconductor, Inc.
List of Figures
Figure 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17
Title
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Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .266 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 267 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .269 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 271 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Port Option Control Register (POCR). . . . . . . . . . . . . . . . . . . 273 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .277 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 277 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . 280 IRQ Option Control Register (IOCR) . . . . . . . . . . . . . . . . . . .281 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . . . .285 Keyboard Status and Control Register (KBSCR) . . . . . . . . . . 288 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . . 289 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . .294 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . .295 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . .299 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 303 Break Module I/O Register Summary . . . . . . . . . . . . . . . . . . . 303 Break Status and Control Register (BRKSCR). . . . . . . . . . . . 305 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . . 306 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . . 306 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . 307 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . 308 32-Pin LQFP (Case #873A) . . . . . . . . . . . . . . . . . . . . . . . . . .320
Freescale Semiconductor, Inc...
15-1 15-2 15-3 15-4 16-1 16-2 16-3 16-4 17-1 17-2 17-3 18-1 18-2 19-1 19-2 19-3 19-4 19-5 19-6 19-7 21-1
MC68HC908JG16 -- Rev. 1.0 MOTOROLA List of Figures For More Information On This Product, Go to: www.freescale.com
Technical Data 25
Freescale Semiconductor, Inc.
List of Figures
Freescale Semiconductor, Inc...
Technical Data 26 List of Figures For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Technical Data -- MC68HC908JG16
List of Tables
Table 1-1
Title
Page
Summary of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Summary of FLASH Routine Variables . . . . . . . . . . . . . . . . . . 66 ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SIM Module Signal Name Conventions . . . . . . . . . . . . . . . . . . 97 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Registers not Affected by Normal Reset. . . . . . . . . . . . . . . . . 105 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Mode Entry Requirements and Options . . . . . . . . . . . . . . . . . 124 Monitor Mode Vector Differences . . . . . . . . . . . . . . . . . . . . . .126 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 127 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 129 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 130 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 130 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 131 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . .131 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 132 Monitor Mode Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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2-1 4-1 4-2 4-3 4-4 4-5 6-1 6-2 8-1 8-2 8-3 8-4 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10
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Technical Data 27
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List of Tables
Table 10-1 10-2 10-3 11-1 11-2 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 13-1 13-2 14-1 14-2 14-3 14-4 14-5 14-6 16-1 22-1 Title Page
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . .156 USB Module Pin Name Conventions . . . . . . . . . . . . . . . . . . .162 Supported Packet Identifiers. . . . . . . . . . . . . . . . . . . . . . . . . . 169 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Stop Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .230 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . 244 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . . 257 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
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Technical Data 28
MC68HC908JG16 -- Rev. 1.0 List of Tables For More Information On This Product, Go to: www.freescale.com MOTOROLA
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Technical Data -- MC68HC908JG16
Section 1. General Description
1.1 Contents
1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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1.3 1.4 1.5
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6.1 Power Supply Pins (VDD, VSS) . . . . . . . . . . . . . . . . . . . . . . .33 1.6.2 Voltage Regulator Output Pin (VREG). . . . . . . . . . . . . . . . . . 34 1.6.3 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 35 1.6.4 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.5 External Interrupt Pins (IRQ, PTE4/D-) . . . . . . . . . . . . . . . .35 1.6.6 Analog Power Supply Pins (VDDA, VSSA) . . . . . . . . . . . . . . . 35 1.6.7 Analog Voltage Regulator Out (VREGA) . . . . . . . . . . . . . . . . 35 1.6.8 Port A Input/Output (I/O) Pins (PTA7/KBA7/AD7-PTA0/KBA0/AD0) . . . . . . . . . . . . . . . 36 1.6.9 Port B I/O Pins (PTB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.10 Port C I/O Pins (PTC1/RxD, PTC0/TxD) . . . . . . . . . . . . . . . 36 1.6.11 Port D I/O Pins (PTD3-PTD0) . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.12 Port E I/O Pins (PTE4/D-, PTE3/D+, PTE2/T2CH01, PTE1/T1CH01, PTE0/TCLK). . . . . . . . . . . . . . . . . . . . . . 36
1.2 Introduction
The MC68HC908JG16 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy.
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Technical Data 29
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General Description 1.3 Features
Features of the MC68HC908JG16 MCU include the following: * * * * High-performance M68HC08 architecture Fully upward-compatible object code with M6805, M146805, and M68HC05 families Low-power design; fully static with stop and wait modes 6-MHz internal bus frequency 16,384 bytes of on-chip FLASH memory with security1 feature 384 bytes of on-chip random access memory (RAM) Up to 20 general-purpose input/output (I/O) pins, including: - 15 shared-function I/O pins - 8-bit keyboard interrupt port - 10mA high current drive for PS/2 connection on 2 pins (with USB module disabled) - 5 dedicated I/O pins, with 25mA direct drive for infrared LED on 2 pins and 10mA direct drive for normal LED on 2 pins * Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture, output compare, PWM capability on each channel, and external clock input option (TCLK) Universal Serial Bus specification 2.0 low-speed functions: - 1.5Mbps data rate - On-chip 3.3V regulator - Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer - Endpoint 1 with 8-byte transmit buffer - Endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer * * Serial communications interface module (SCI) 8-channel, 8-bit analog-to-digital converter (ADC)
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* * *
*
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users.
Technical Data 30 General Description For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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General Description MCU Block Diagram
* *
In-circuit programming capability using USB communication or standard serial link on PTA0 pin System protection features: - Optional computer operating properly (COP) reset - Optional Low-voltage detection with reset - Illegal opcode detection with reset - Illegal address detection with reset
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* * *
Master reset pin with internal pull-up and power-on reset IRQ interrupt pin with internal pull-up and schmitt-trigger input 32-pin low-profile quad flat pack (LQFP)
Features of the CPU08 include the following: * * * * * * * * * * Enhanced HC05 programming model Extensive loop control functions 16 addressing modes (eight more than the HC05) 16-bit index register and stack pointer Memory-to-memory data transfers Fast 8 x 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (BCD) instructions Optimization for controller applications Third party C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908JG16.
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Technical Data 31
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DDRA PTA
General Description
SERIAL COMMUNICATIONS INTERFACE MODULE LOW VOLTAGE INHIBIT MODULE DDRC PTC
USER RAM -- 384 BYTES
MONITOR ROM -- 1,472 BYTES POWER-ON RESET MODULE
DDRB
PTB
(2)
RST
SYSTEM INTEGRATION MODULE
2-CHANNEL TIMER INTERFACE MODULE 1
DDRD
PTD
VREFH VREFL 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE
DDRE
PTE
Technical Data
M68HC08 CPU ARITHMETIC/LOGIC UNIT (ALU) KEYBOARD INTERRUPT MODULE PTA7/KBA7/AD7 (3) : PTA0/KBA0/AD0 BREAK MODULE PTB0 (3) PTC1/RxD (3) PTC0/TxD (3) OSCILLATOR COMPUTER OPERATING PROPERLY MODULE PTD3-PTD0 (4) IRQ MODULE 2-CHANNEL TIMER INTERFACE MODULE 2 PTE4/D- (3), (4) PTE3/D+ (3), (4) USB MODULE USB ENDPOINT 0, 1, 2 PTE2/T2CH01 (3) PTE1/T1CH01 (3) PTE0/TCLK (3) LS USB TRANSCEIVER POWER AND INTERNAL VOLTAGE REGULATORS (1) Pins have 3V logic. (2) Pins have integrated pullup device. (3) Pins have software configurable pull-up device. (4) Pins are open-drain when configured as output.
32
CPU REGISTERS
CONTROL AND STATUS REGISTERS -- 64 BYTES
USER FLASH MEMORY -- 16,384 BYTES
USER FLASH VECTORS -- 48 BYTES
(1)
OSC1
(1) OSC2
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(3)
IRQ
VDD VSS VREG (3.3V)
VDDA VSSA VREGA (3.3V)
MC68HC908JG16 -- Rev. 1.0
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Figure 1-1. MC68HC908JG16 MCU Block Diagram
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General Description Pin Assignments
1.5 Pin Assignments
PTA0/KBA0/AD0 26
25 PTA1/KBA1/AD1 24 PTA2/KBA2/AD2
32 OSC1
VREGA
VDDA
VSSA 28
VSS
31
30
29
OSC2 1
27
RST
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VREG VDD PTD0 PTD1 PTD2 PTD3 PTE1/T1CH01 8
2 3 4 5 6 7 10 11 12 13 14 15
23 22 21 20 19 18
PTA3/KBA3/AD3 VREFH VREFL PTB0 PTE0/TCLK PTE2/T2CH01
17 PTA4/KBA4/AD4
Figure 1-2. 32-Pin LQFP Pin Assignment
1.6 Pin Functions
Description of pin functions are provided here.
1.6.1 Power Supply Pins (VDD, VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take care to provide power supply bypassing at the MCU as shown in Figure 1-3.
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PTA5/KBA5/AD5 16
PTE3/D+ 9
PTE4/D-
PTA7/KBA7/AD7
PTA6/KBA6/AD6
IRQ
PTC1/RxD
PTC0/TxD
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General Description
Place the bypass capacitors as close to the MCU power pins as possible. Use high-frequency-response ceramic capacitors for CBYPASS. CBULK are optional bulk current bypass capacitors for use in applications that require the port pins to source high current levels.
MCU
VDD VSS
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CBYPASS 0.1 F + CBULK
VDD NOTE: Values shown are typical values.
Figure 1-3. Power Supply Bypassing
1.6.2 Voltage Regulator Output Pin (VREG) VREG is the 3.3V output of the on-chip voltage regulator. VREG is used internally for the MCU operation and the USB data driver. It is also used to supply the voltage for the external pullup resistor required on the USB's D- line. The VREG pin requires an external bulk capacitor 4.7F or larger and a 0.1F ceramic bypass capacitor as Figure 1-4 shows. Place the bypass capacitors as close to the VREG pin as possible.
VREG
MCU
VSS
CREGBYPASS 0.1 F + CREGBULK > 4.7 F
Figure 1-4. Regulator Supply Capacitor Configuration
Technical Data 34 General Description For More Information On This Product, Go to: www.freescale.com MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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General Description Pin Functions
1.6.3 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit.
1.6.4 External Reset Pin (RST) A logic zero on the RST pin forces the MCU to a known start-up state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. The RST pin contains an internal pullup device to VDD. (See Section 8. System Integration Module (SIM).)
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1.6.5 External Interrupt Pins (IRQ, PTE4/D-) IRQ is an asynchronous external interrupt pin. IRQ is also the pin to enter Monitor mode. The IRQ pin contains a software configurable pullup device to VDD. PTE4/D- can be programmed to trigger the IRQ interrupt. (See Section 15. External Interrupt (IRQ).)
1.6.6 Analog Power Supply Pins (VDDA, VSSA) VDDA and VSSA are the power supply and ground pins for the analog portion of the MCU. Connect VDDA to the same voltage potential as VDD. Connect VSSA to the same voltage potential as VSS. Decoupling of these pins should be as per the digital supply.
1.6.7 Analog Voltage Regulator Out (VREGA) VREGA is the 3.3V output of the second on-chip voltage regulator. VREGA is used for ADC operation. Decoupling of this pin should be as per the digital VREG.
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General Description
1.6.8 Port A Input/Output (I/O) Pins (PTA7/KBA7/AD7-PTA0/KBA0/AD0) Port A is a 8-bit special function port that shares its pins with the analogto-digital converter and keyboard interrupt module. (See Section 14. Input/Output (I/O) Ports, Section 13. Analog-to-Digital Converter (ADC), and Section 16. Keyboard Interrupt Module (KBI).) Each pin contains a software configurable pullup device to VDD when the pin is configured as an input. (See 14.8 Port Options.) 1.6.9 Port B I/O Pins (PTB0) Port B is an 1-bit general-purpose bidirectional I/O port pin and contains a software configurable pullup device to VDD when the pin is configured as an input. (See Section 14. Input/Output (I/O) Ports and 14.8 Port Options.)
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1.6.10 Port C I/O Pins (PTC1/RxD, PTC0/TxD) Port C is a 2-bit special function port that shares its pins with the SCI module. (See Section 14. Input/Output (I/O) Ports.) Each pin contains a software configurable pullup device to VDD when the pin is configured as an input. (See 14.8 Port Options.) 1.6.11 Port D I/O Pins (PTD3-PTD0) PTD3-PTD0 are general-purpose bidirectional I/O port pins; open-drain when configured as output. (See Section 14. Input/Output (I/O) Ports.) PTD3-PTC2 are software configurable to be 10mA sink pins for direct LED connections. PTD1-PTD0 are software configurable to be 25mA sink pins for direct infrared LED connections. (See 14.8 Port Options.) 1.6.12 Port E I/O Pins (PTE4/D-, PTE3/D+, PTE2/T2CH01, PTE1/T1CH01, PTE0/TCLK) Port E is a 5-bit special function port that shares two of its pins with the USB module and three of its pins with the two timer interface modules. Each PTE2-PTE0 pin contains a software configurable pullup device to VDD when the pin is configured as an input or output.
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General Description Pin Functions
When the USB module is disabled, the PTE4 and PTE3 pins are general-purpose bidirectional I/O port pins with 10mA sink capability. Each pin is open-drain when configured as an output; and each pin contains a software configurable 5k pullup to VDD when configured as an input. The PTE4 pin can also be enabled to trigger the IRQ interrupt. When the USB module is enabled, the PTE4/D- and PTE3/D+ pins become the USB module D- and D+ pins. The USB D- pin contains a 1.5k software configurable pullup device to VREG. (See Section 10. Timer Interface Module (TIM), Section 11. Universal Serial Bus Module (USB) and Section 14. Input/Output (I/O) Ports.)
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NOTE:
Any unused inputs and I/O ports should be tied to an appropriate logic level (either VDD or VSS). Although the I/O ports of the MC68HC908JG16 do not require termination, termination is recommended to reduce the possibility of static damage. Summary of the pin functions are provided in Table 1-1. Table 1-1. Summary of Pin Functions
PIN NAME VDD VSS VREG RST Power supply.
PIN DESCRIPTION
IN/OUT IN OUT OUT IN/OUT IN IN IN OUT IN OUT OUT
VOLTAGE LEVEL 4.0 to 5.5V 0V VREG (3.3V) VDD VDD VREG to VTST VREG VREG 4.0 to 5.5V 0V VREGA (3.3V)
Power supply ground. 3.3V regulated output from MCU. Reset input, active low. With internal pull-up and schmitt trigger input. External IRQ pin; with programmable internal pull-up and schmitt trigger input. Used for mode entry selection.
IRQ
OSC1 OSC2 VDDA VSSA VREGA
Crystal oscillator input. Crystal oscillator output; inverting of OSC1 signal. Analog power supply. Analog power supply ground. 3.3V regulated output from MCU.
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General Description
Table 1-1. Summary of Pin Functions
PIN NAME PIN DESCRIPTION 8-bit general purpose I/O port. PTA0/KBA0/AD0 : PTA7/KBA7/AD7 Pins as keyboard interrupts, KBA0-KBA7. Each pin has programmable internal pullup when configured as input. Each pin can be configured as ADC input channel. IN/OUT IN/OUT IN IN IN IN/OUT IN OUT IN IN OUT OUT OUT IN/OUT IN/OUT IN IN/OUT IN/OUT IN OUT IN IN/OUT IN/OUT IN VOLTAGE LEVEL VDD VDD VDD VSSA to VREGA VDD VDD VDD VDD VDD VREG or VDD VREG or VDD VREG or VDD VDD VDD VDD VDD VDD VDD VREG or VDD VDD VREG VREG VDD
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2-bit general purpose I/O port. PTC0/TxD PTC1/RxD Each pin has programmable internal pull-up device. PTC0 as TxD of SCI module. PTC1 as RxD of SCI module. 4-bit general purpose I/O port; open-drain when configured as output. PTD0-PTD3 PTD0-PTD1 have configurable 25mA sink for infrared LED. PTD2-PTD3 have configurable 10mA sink for LED. PTE0-PTE2 are general purpose I/O lines. PTE0/TCLK PTE1/T1CH01 PTE2/T2CH01 PTE0-PTE2 have programmable internal pullup when configured as input or output. PTE0 as TCLK of TIM1 and TIM2. PTE1 as T1CH01 of TIM1. PTE2 as T2CH01 of TIM2. PTE3-PTE4 general purpose I/O lines; open-drain when configured as output. PTE3/D+ PTE4/D- PTE3-PTE4 have programmable internal pullup when configured as input. PTE3 as D+ of USB module. PTE4 as D- of USB module. PTE4 as additional IRQ interrupt.
Technical Data 38 General Description For More Information On This Product, Go to: www.freescale.com
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Technical Data -- MC68HC908JG16
Section 2. Memory Map
2.1 Contents
2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 39 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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2.3 2.4 2.5
2.2 Introduction
The CPU08 can address 64k-bytes of memory space. The memory map, shown in Figure 2-1, includes: * * * * 16,384 bytes of FLASH memory 384 bytes of random-access memory (RAM) 48 bytes of user-defined vectors 1,024 + 448 bytes of monitor ROM
2.3 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled. In the memory map (Figure 2-1) and in register figures in this document, unimplemented locations are shaded.
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Memory Map 2.4 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In the Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R.
2.5 Input/Output (I/O) Section
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Most of the control, status, and data registers are in the zero page area of $0000-$007F. Additional I/O registers have these addresses: * * * * * * * * * * * * * * * * * $FE00; SIM break status register, SBSR $FE01; SIM reset status register, SRSR $FE02; Reserved $FE03; SIM break flag control register, SBFCR $FE04; Interrupt status register 1, INT1 $FE05; Interrupt status register 2, INT2 $FE06; Interrupt status register 3, INT3 $FE07; Reserved $FE08; FLASH control register, FLCR $FE09; FLASH block protect register, FLBPR $FE0A; Reserved $FE0B; Reserved $FE0C; Break address register high, BRKH $FE0D; Break address register low, BRKL $FE0E; Break status and control register, BRKSCR $FE0F; Reserved $FFFF; COP control register, COPCTL
Data registers are shown in Figure 2-2. Table 2-1 is a list of vector locations.
Technical Data 40 Memory Map For More Information On This Product, Go to: www.freescale.com
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Memory Map Input/Output (I/O) Section
$0000 $007F $0080 $01FF $0200 $B9FF $BA00 $F9FF $FA00 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FFCF $FFD0 $FFFF
I/O Registers 128 Bytes RAM 384 Bytes Unimplemented 47,104 Bytes FLASH Memory 16,384 Bytes Monitor ROM 1 1,024 Bytes SIM Break Status Register (SBSR) SIM Reset Status Register (SRSR) Reserved SIM Break Flag Control Register (SBFCR) Interrupt Status Register 1 (INT1) Interrupt Status Register 2 (INT2) Interrupt Status Register 3 (INT3) Reserved FLASH Control Register (FLCR) FLASH Block Protect Register (FLBPR) Reserved Reserved Break Address Register High (BRKH) Break Address Register Low (BRKL) Break Status and Control Register (BRKSCR) Reserved Monitor ROM 2 448 Bytes FLASH Vectors 48 Bytes
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Figure 2-1. Memory Map
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Technical Data 41
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Memory Map
Addr. $0000
Register Name Read: Port A Data Register Write: (PTA) Reset: Read: Port B Data Register Write: (PTB) Reset: Read: Port C Data Register Write: (PTC) Reset: Read: Port D Data Register Write: (PTD) Reset:
Bit 7 PTA7
6 PTA6
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
Unaffected by reset 0 0 0 0 0 0 0 PTB0
$0001
Unaffected by reset 0 0 0 0 0 0 PTC1 PTC0
$0002
Freescale Semiconductor, Inc...
Unaffected by reset 0 0 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
$0003
Unaffected by reset DDRA6 0 0 0 0 0 0 0 0 DDRA5 0 0 0 0 0 DDRD5 0 0 DDRA4 0 0 0 0 0 DDRD4 0 PTE4 DDRA3 0 0 0 0 0 DDRD3 0 PTE3 DDRA2 0 0 0 0 0 DDRD2 0 PTE2 DDRA1 0 0 0 DDRC1 0 DDRD1 0 PTE1 DDRA0 0
Read: DDRA7 Data Direction Register A $0004 Write: (DDRA) Reset: 0* * DDRA7 bit is reset by POR or LVI reset only. Read: Data Direction Register B $0005 Write: (DDRB) Reset: Read: Data Direction Register C $0006 Write: (DDRC) Reset: Read: Data Direction Register D $0007 Write: (DDRD) Reset: $0008 Read: Port E Data Register Write: (PTE) Reset: 0 0 0 0 0 0 0
DDRB0 0 DDRC0 0 DDRD0 0 PTE0
Unaffected by reset 0 0 0 0 0 0 DDRE4 0 DDRE3 0 DDRE2 0 R DDRE1 0 = Reserved DDRE0 0
Read: Data Direction Register E $0009 Write: (DDRE) Reset: U = Unaffected
X = Indeterminate
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 12)
Technical Data 42 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Memory Map Input/Output (I/O) Section
Addr.
Register Name
Bit 7 TOF 0 0 R
6 TOIE 0 R
5 TSTOP 1 R
4 0 TRST 0 R
3 0 0 R
2 PS2 0 R
1 PS1 0 R
Bit 0 PS0 0 R
Read: Timer 1 Status and Control $000A Register Write: (T1SC) Reset: Read: $000B Reserved Write: Reset: $000C Read: Timer 1 Counter Register High Write: (T1CNTH) Reset: Timer 1 Counter Read: Register Low Write: (T1CNTL) Reset: Timer 1 Counter Modulo Read: Register High Write: (T1MODH) Reset: Timer 1 Counter Modulo Read: Register Low Write: (T1MODL) Reset: Timer 1 Channel 0 Read: Status and Control Write: Register (T1SC0) Reset: Read: Timer 1 Channel 0 Register High Write: (T1CH0H) Reset: Read: Timer 1 Channel 0 Register Low Write: (T1CH0L) Reset: Timer 1 Channel 1 Read: Status and Control Write: Register (T1SC1) Reset: U = Unaffected
Bit15 0 Bit7 0 Bit15 1 Bit7 1 CH0F 0 0 Bit15
Bit14 0 Bit6 0 Bit14 1 Bit6 1 CH0IE 0 Bit14
Bit13 0 Bit5 0 Bit13 1 Bit5 1 MS0B 0 Bit13
Bit12 0 Bit4 0 Bit12 1 Bit4 1 MS0A 0 Bit12
Bit11 0 Bit3 0 Bit11 1 Bit3 1 ELS0B 0 Bit11
Bit10 0 Bit2 0 Bit10 1 Bit2 1 ELS0A 0 Bit10
Bit9 0 Bit1 0 Bit9 1 Bit1 1 TOV0 0 Bit9
Bit8 0 Bit0 0 Bit8 1 Bit0 1 CH0MAX 0 Bit8
Freescale Semiconductor, Inc...
$000D
$000E
$000F
$0010
$0011
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$0012
Indeterminate after reset CH1F 0 0 CH1IE 0 CH01IE 0 MS1A 0 ELS1B 0 ELS1A 0 R TOV1 0 = Reserved CH1MAX 0
$0013
X = Indeterminate
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 12)
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com
Technical Data 43
Freescale Semiconductor, Inc.
Memory Map
Addr. $0014
Register Name Read: Timer 1 Channel 1 Register High Write: (T1CH1H) Reset: Read: Timer 1 Channel 1 Register Low Write: (T1CH1L) Reset: Read: Keyboard Status and Control Register Write: (KBSCR) Reset:
Bit 7 Bit15
6 Bit14
5 Bit13
4 Bit12
3 Bit11
2 Bit10
1 Bit9
Bit 0 Bit8
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$0015
Indeterminate after reset 0 0 KBIE7 0 0 0 KBIE6 0 0 RSTFR 0 STALL2 0 0 TX1STR 0 0 0 0 0 0 0 0 0 0 0 0 KBIE5 0 0 TXD2FR 0 TX2E 0 0 0 KBIE4 0 0 RXD2FR 0 RX2E 0 KEYF 0 KBIE3 0 0 0 TP2SIZ3 0 0 0 0 0 0 0 PTE3P 0 0 ACKK 0 KBIE2 0 0 0 TP2SIZ2 0 IMASKK 0 KBIE1 0 0 0 TP2SIZ1 0 MODEK 0 KBIE0 0 0 RXD0FR 0 TP2SIZ0 0
$0016
Freescale Semiconductor, Inc...
Keyboard Interrupt Enable Read: $0017 Register Write: (KBIER) Reset: $0018
Read: 0 USB Interrupt Register 2 Write: EOPFR (UIR2) Reset: 0 Read: T2SEQ USB Control Register 2 Write: (UCR2) Reset: 0 Read: USB Control Register 3 Write: (UCR3) Reset: Read: USB Control Register 4 Write: (UCR4) Reset: Read: IRQ Option Control Register Write: (IOCR) Reset: TX1ST
TDX1FR RESUMFR TXD0FR
$0019
$001A
OSTALL0 ISTALL0 0 0 0 0 0 0 0 0 0 0 PTE4P 0
PULLEN ENABLE2 ENABLE1 0* 0 0
* PULLEN bit is reset by POR or LVI reset only. $001B FUSBO 0 PTE4IF 0 PCP 0 R FDP 0 PTE4IE 0 PBP 0 = Reserved FDM 0 IRQPD 0 PAP 0
$001C
$001D
Read: Port Option Control PTE20P Register Write: (POCR) Reset: 0 U = Unaffected
PTDLDD PTDILDD 0 0
X = Indeterminate
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 12)
Technical Data 44 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Memory Map Input/Output (I/O) Section
Addr. $001E
Register Name Read: IRQ Status and Control Register Write: (INTSCR) Reset: Read: Configuration Register Write: (CONFIG) Reset:
Bit 7 0 0 LVIDR 0*
6 0 0 LVI5OR3 0*
5 0 0 URSTD 0*
4 0 0 LVID 0*
3 IRQF 0 SSREC 0
2 0 ACK 0 COPRS 0
1 IMASK 0 STOP 0
Bit 0 MODE 0 COPD 0
$001F
One-time writable register after each reset. * LVIDR, LVI5OR3, URSTD, and LVID, are reset by POR or LVI reset only.
Freescale Semiconductor, Inc...
$0020
Read: UE0R07 USB Endpoint 0 Data Register 0 Write: UE0T07 (UE0D0) Reset: Read: UE0R17 USB Endpoint 0 Data Register 1 Write: UE0T17 (UE0D1) Reset: Read: UE0R27 USB Endpoint 0 Data Register 2 Write: UE0T27 (UE0D2) Reset: Read: UE0R37 USB Endpoint 0 Data Register 3 Write: UE0T37 (UE0D3) Reset: Read: UE0R47 USB Endpoint 0 Data Register 4 Write: UE0T47 (UE0D4) Reset: Read: UE0R57 USB Endpoint 0 Data Register 5 Write: UE0T57 (UE0D5) Reset: Read: UE0R67 USB Endpoint 0 Data Register 6 Write: UE0T67 (UE0D6) Reset: Read: UE0R77 USB Endpoint 0 Data Register 7 Write: UE0T77 (UE0D7) Reset: U = Unaffected
UE0R06 UE0T06 UE0R16 UE0T16 UE0R26 UE0T26 UE0R36 UE0T36 UE0R46 UE0T46 UE0R56 UE0T56 UE0R66 UE0T66 UE0R76 UE0T76
UE0R05 UE0T05 UE0R15 UE0T15 UE0R25 UE0T25 UE0R35 UE0T35 UE0R45 UE0T45 UE0R55 UE0T55 UE0R65 UE0T65 UE0R75 UE0T75
UE0R04 UE0T04 UE0R14 UE0T14 UE0R24 UE0T24 UE0R34 UE0T34 UE0R44 UE0T44 UE0R54 UE0T54 UE0R64 UE0T64 UE0R74 UE0T74
UE0R03 UE0T03 UE0R13 UE0T13 UE0R23 UE0T23 UE0R33 UE0T33 UE0R43 UE0T43 UE0R53 UE0T53 UE0R63 UE0T63 UE0R73 UE0T73
UE0R02 UE0T02 UE0R12 UE0T12 UE0R22 UE0T22 UE0R32 UE0T32 UE0R42 UE0T42 UE0R52 UE0T52 UE0R62 UE0T62 UE0R72 UE0T72
UE0R01 UE0T01 UE0R11 UE0T11 UE0R21 UE0T21 UE0R31 UE0T31 UE0R41 UE0T41 UE0R51 UE0T51 UE0R61 UE0T61 UE0R71 UE0T71
UE0R00 UE0T00 UE0R10 UE0T10 UE0R20 UE0T20 UE0R30 UE0T30 UE0R40 UE0T40 UE0R50 UE0T50 UE0R60 UE0T60 UE0R70 UE0T70
Unaffected by reset
$0021
Unaffected by reset
$0022
Unaffected by reset
$0023
Unaffected by reset
$0024
Unaffected by reset
$0025
Unaffected by reset
$0026
Unaffected by reset
$0027
Unaffected by reset = Unimplemented R = Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 12)
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com Technical Data 45
Freescale Semiconductor, Inc.
Memory Map
Addr. $0028
Register Name
Bit 7
6 UE1T06
5 UE1T05
4 UE1T04
3 UE1T03
2 UE1T02
1 UE1T01
Bit 0 UE1T00
Read: USB Endpoint 1 Data Register 0 Write: UE1T07 (UE1D0) Reset: Read: USB Endpoint 1 Data Register 1 Write: UE1T17 (UE1D1) Reset: Read: USB Endpoint 1 Data Register 2 Write: UE1T27 (UE1D2) Reset: USB Endpoint 1 Data Read: Register 3 Write: UE1T37 (UE1D3) Reset: USB Endpoint 1 Data Read: Register 4 Write: UE1T47 (UE1D4) Reset: USB Endpoint 1 Data Read: Register 5 Write: UE1T57 (UE1D5) Reset: USB Endpoint 1 Data Read: Register 6 Write: UE1T67 (UE1D6) Reset: USB Endpoint 1 Data Read: Register 7 Write: UE1T77 (UE1D7) Reset: USB Endpoint 2 Data Read: UE2R07 Register 0 Write: UE2T07 (UE2D0) Reset: USB Endpoint 2 Data Read: UE2R17 Register 1 Write: UE2T17 (UE2D1) Reset: U = Unaffected
Unaffected by reset UE1T16 UE1T15 UE1T14 UE1T13 UE1T12 UE1T11 UE1T10
$0029
Unaffected by reset UE1T26 UE1T25 UE1T24 UE1T23 UE1T22 UE1T21 UE1T20
$002A
Freescale Semiconductor, Inc...
Unaffected by reset UE1T36 UE1T35 UE1T34 UE1T33 UE1T32 UE1T31 UE1T30
$002B
Unaffected by reset UE1T46 UE1T45 UE1T44 UE1T43 UE1T42 UE1T41 UE1T40
$002C
Unaffected by reset UE1T56 UE1T55 UE1T54 UE1T53 UE1T52 UE1T51 UE1T50
$002D
Unaffected by reset UE1T66 UE1T65 UE1T64 UE1T63 UE1T62 UE1T61 UE1T60
$002E
Unaffected by reset UE1T76 UE2R06 UE2T06 UE2R16 UE2T16 UE1T75 UE2R05 UE2T05 UE2R15 UE2T15 UE1T74 UE2R04 UE2T04 UE2R14 UE2T14 UE1T73 UE2R03 UE2T03 UE2R13 UE2T13 UE1T72 UE2R02 UE2T02 UE2R12 UE2T12 UE1T71 UE2R01 UE2T01 UE2R11 UE2T11 UE1T70 UE2R00 UE2T00 UE2R10 UE2T10
$002F
Unaffected by reset
$0030
Unaffected by reset
$0031
Unaffected by reset = Unimplemented R = Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 12)
Technical Data 46 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Memory Map Input/Output (I/O) Section
Addr. $0032
Register Name
Bit 7
6 UE2R26 UE2T26 UE2R36 UE2T36 UE2R46 UE2T46 UE2R56 UE2T56 UE2R66 UE2T66 UE2R76 UE2T76
5 UE2R25 UE2T25 UE2R35 UE2T35 UE2R45 UE2T45 UE2R55 UE2T55 UE2R65 UE2T65 UE2R75 UE2T75
4 UE2R24 UE2T24 UE2R34 UE2T34 UE2R44 UE2T44 UE2R54 UE2T54 UE2R64 UE2T64 UE2R74 UE2T74
3 UE2R23 UE2T23 UE2R33 UE2T33 UE2R43 UE2T43 UE2R53 UE2T53 UE2R63 UE2T63 UE2R73 UE2T73
2 UE2R22 UE2T22 UE2R32 UE2T32 UE2R42 UE2T42 UE2R52 UE2T52 UE2R62 UE2T62 UE2R72 UE2T72
1 UE2R21 UE2T21 UE2R31 UE2T31 UE2R41 UE2T41 UE2R51 UE2T51 UE2R61 UE2T61 UE2R71 UE2T71
Bit 0 UE2R20 UE2T20 UE2R30 UE2T30 UE2R40 UE2T40 UE2R50 UE2T50 UE2R60 UE2T60 UE2R70 UE2T70
Read: UE2R27 USB Endpoint 2 Data Register 2 Write: UE2T27 (UE2D2) Reset: Read: UE2R37 USB Endpoint 2 Data Register 3 Write: UE2T37 (UE2D3) Reset: Read: UE2R47 USB Endpoint 2 Data Register 4 Write: UE2T47 (UE2D4) Reset: USB Endpoint 2 Data Read: UE2R57 Register 5 Write: UE2T57 (UE2D5) Reset: USB Endpoint 2 Data Read: UE2R67 Register 6 Write: UE2T67 (UE2D6) Reset: USB Endpoint 2 Data Read: UE2R77 Register 7 Write: UE2T77 (UE2D7) Reset: Read: USBEN USB Address Register Write: (UADDR) Reset: 0* Read: USB Interrupt Register 0 Write: (UIR0) Reset: Read: USB Interrupt Register 1 Write: (UIR1) Reset:
Unaffected by reset
$0033
Unaffected by reset
$0034
Freescale Semiconductor, Inc...
Unaffected by reset
$0035
Unaffected by reset
$0036
Unaffected by reset
$0037
Unaffected by reset UADD6 0 UADD5 0 UADD4 0 UADD3 0 UADD2 0 0 0 RESUMF 0 TP0SIZ2 0 R UADD1 0 UADD0 0
$0038
* USBEN bit is reset by POR or LVI reset only. $0039 EOPIE 0 EOPF 0 SUSPND 0 RSTF 0 0 0 TXD2IE 0 TXD2F 0 TX0E 0 RXD2IE 0 RXD2F 0 RX0E 0 TXD1IE 0 TXD1F 0 TP0SIZ3 0 TXD0IE 0 TXD0F 0 TP0SIZ1 0 = Reserved RXD0IE 0 RXD0F 0 TP0SIZ0 0
$003A
$003B
Read: T0SEQ USB Control Register 0 Write: (UCR0) Reset: 0 U = Unaffected
X = Indeterminate
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 12)
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com
Technical Data 47
Freescale Semiconductor, Inc.
Memory Map
Addr. $003C
Register Name
Bit 7
6 STALL1 0 SETUP
5 TX1E 0 0
4
3
2 TP1SIZ2 0 RP0SIZ2
1 TP1SIZ1 0 RP0SIZ1
Bit 0 TP1SIZ0 0 RP0SIZ0
Read: T1SEQ USB Control Register 1 Write: (UCR1) Reset: 0 Read: R0SEQ USB Status Register 0 Write: (USR0) Reset: Read: R2SEQ USB Status Register 1 Write: (USR1) Reset: U Read: Unimplemented Write: TOF 0 0 R
FRESUM TP1SIZ3 0 0 0 RP0SIZ3
$003D
Unaffected by reset TXACK 0 TXNAK 0 TXSTL 0 RP2SIZ3 U RP2SIZ2 U RP2SIZ1 U RP2SIZ0 U
$003E
Freescale Semiconductor, Inc...
$003F
Timer 2 Status and Control Read: $0040 Register Write: (T2SC) Reset: Read: $0041 Reserved Write: Reset: $0042 Timer 2 Counter Read: Register High Write: (T2CNTH) Reset: Timer 2 Counter Read: Register Low Write: (T2CNTL) Reset: Timer 2 Counter Modulo Read: Register High Write: (T2MODH) Reset: Timer 2 Counter Modulo Read: Register Low Write: (T2MODL) Reset: U = Unaffected
TOIE 0 R
TSTOP 1 R
0 TRST 0 R
0 0 R
PS2 0 R
PS1 0 R
PS0 0 R
Bit15 0 Bit7 0 Bit15 1 Bit7 1
Bit14 0 Bit6 0 Bit14 1 Bit6 1
Bit13 0 Bit5 0 Bit13 1 Bit5 1
Bit12 0 Bit4 0 Bit12 1 Bit4 1
Bit11 0 Bit3 0 Bit11 1 Bit3 1
Bit10 0 Bit2 0 Bit10 1 Bit2 1 R
Bit9 0 Bit1 0 Bit9 1 Bit1 1 = Reserved
Bit8 0 Bit0 0 Bit8 1 Bit0 1
$0043
$0044
$0045
X = Indeterminate
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 12)
Technical Data 48 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Memory Map Input/Output (I/O) Section
Addr.
Register Name Timer 2 Channel 0 Read: Status and Control Write: Register (T2SC0) Reset: Read: Timer 2 Channel 0 Register High Write: (T2CH0H) Reset: Read: Timer 2 Channel 0 Register Low Write: (T2CH0L) Reset: Timer 2 Channel 1 Read: Status and Control Write: Register (T2SC1) Reset: Read: Timer 2 Channel 1 Register High Write: (T2CH1H) Reset: Read: Timer 2 Channel 1 Register Low Write: (T2CH1L) Reset: Read: Reserved Write: Reset: Read:
Bit 7 CH0F 0 0 Bit15
6 CH0IE 0 Bit14
5 MS0B 0 Bit13
4 MS0A 0 Bit12
3 ELS0B 0 Bit11
2 ELS0A 0 Bit10
1 TOV0 0 Bit9
Bit 0 CH0MAX 0 Bit8
$0046
$0047
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$0048
Freescale Semiconductor, Inc...
Indeterminate after reset CH1F 0 0 Bit15 CH1IE 0 Bit14 CH01IE 0 Bit13 MS1A 0 Bit12 ELS1B 0 Bit11 ELS1A 0 Bit10 TOV1 0 Bit9 CH1MAX 0 Bit8
$0049
$004A
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$004B
Indeterminate after reset R R R R R R R R
$004C
$004D
Reserved Write: Reset: Read:
R
R
R
R
R
R
R
R
$004E
Reserved Write: Reset: Read:
R
R
R
R
R
R
R
R
$004F
Reserved Write: Reset: U = Unaffected
R
R
R
R
R
R
R
R
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 12)
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com
Technical Data 49
Freescale Semiconductor, Inc.
Memory Map
Addr. $0050
Register Name Read: Reserved Write: Reset: Read:
Bit 7 R
6 R
5 R
4 R
3 R
2 R
1 R
Bit 0 R
$0051
Reserved Write: Reset: Read:
R
R
R
R
R
R
R
R
$0052
Reserved Write: Reset: Read:
R
R
R
R
R
R
R
R
Freescale Semiconductor, Inc...
$0053
Reserved Write: Reset: Read:
R
R
R
R
R
R
R
R
$0054
Reserved Write: Reset: Read:
R
R
R
R
R
R
R
R
$0055
Reserved Write: Reset: Read:
R
R
R
R
R
R
R
R
$0056
Reserved Write: Reset: Read:
R
R
R
R
R
R
R
R
$0057
Reserved Write: Reset: Read:
R
R
R
R
R
R
R
R
$0058
Reserved Write: Reset: Read:
R
R
R
R
R
R
R
R
$0059
Reserved Write: Reset: U = Unaffected
R
R
R
R
R
R
R
R
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 12)
Technical Data 50 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Memory Map Input/Output (I/O) Section
Addr. $005A
Register Name
Bit 7
6 ENSCI 0 TCIE 0 T8 U TC 1 0 0 R6 T6 U 0 0 AIEN 0 AD6
5 TXINV 0 SCRIE 0 DMARE 0 SCRF 0 0 0 R5 T5 U SCP1 0 ADCO 0 AD5
4 M 0 ILIE 0 DMATE 0 IDLE 0 0 0 R4 T4 U SCP0 0 ADCH4 1 AD4
3 WAKE 0 TE 0 ORIE 0 OR 0 0 0 R3 T3 U R
2 ILTY 0 RE 0 NEIE 0 NF 0 0 0 R2 T2 U SCR2 0
1 PEN 0 RWU 0 FEIE 0 FE 0 BKF 0 R1 T1 U SCR1 0 ADCH1 1 AD1
Bit 0 PTY 0 SBK 0 PEIE 0 PE 0 RPF 0 R0 T0 U SCR0 0 ADCH0 1 AD0
Read: LOOPS SCI Control Register 1 Write: (SCC1) Reset: 0 Read: SCI Control Register 2 Write: (SCC2) Reset: Read: SCI Control Register 3 Write: (SCC3) Reset: Read: SCI Status Register 1 Write: (SCS1) Reset: Read: SCI Status Register 2 Write: (SCS2) Reset: Read: SCI Data Register Write: (SCDR) Reset: Read: SCI Baud Rate Register Write: (SCBR) Reset: ADC Status and Control Read: Register Write: (ADSCR) Reset: Read: ADC Data Register Write: (ADR) Reset: SCTIE 0 R8 U SCTE 1 0 0 R7 T7 U 0 0 COCO 0 AD7
$005B
$005C
Freescale Semiconductor, Inc...
$005D
$005E
$005F
$0060
$0061
ADCH3 1 AD3
ADCH2 1 AD2
$0062
Indeterminate after reset ADIV2 0 ADIV1 0 ADIV0 0 0 0 0 0 0 0 R 0 0 = Reserved 0 0
Read: ADC Input Clock Register $0063 Write: (ADICLK) Reset: U = Unaffected
X = Indeterminate
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 12)
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com
Technical Data 51
Freescale Semiconductor, Inc.
Memory Map
Addr. $0064 to $007F
Register Name Read: Unimplemented Write: Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Note: Writing a logic 0 clears SBSW.
R
R
R
R
R
R
SBSW Note 0
R
Freescale Semiconductor, Inc...
Read: SIM Reset Status Register $FE01 Write: (SRSR) POR: Read: $FE02 Reserved Write: Reset: $FE03 Read: SIM Break Flag Control Register Write: (SBFCR) Reset:
POR 1 R
PIN 0 R
COP 0 R
ILOP 0 R
ILAD 0 R
USB 0 R
LVI 0 R
0 0 R
BCFE 0 IF6 R 0 IF14 R 0 0 R 0 R
R
R
R
R
R
R
R
Read: Interrupt Status Register 1 $FE04 Write: (INT1) Reset: Read: Interrupt Status Register 2 $FE05 Write: (INT2) Reset: Read: Interrupt Status Register 3 $FE06 Write: (INT3) Reset: Read: $FE07 Reserved Write: Reset: U = Unaffected
IF5 R 0 IF13 R 0 0 R 0 R
IF4 R 0 IF12 R 0 0 R 0 R
IF3 R 0 IF11 R 0 0 R 0 R
IF2 R 0 IF10 R 0 0 R 0 R
IF1 R 0 IF9 R 0 0 R 0 R
0 R 0 IF8 R 0 0 R 0 R
0 R 0 IF7 R 0 IF15 R 0 R
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 11 of 12)
Technical Data 52 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Memory Map Input/Output (I/O) Section
Addr. $FE08
Register Name Read: FLASH Control Register Write: (FLCR) Reset: Read: FLASH Block Protect Register Write: (FLBPR) Reset: Read: Reserved Write: Reset: Read:
Bit 7 0 0 BPR7 0 R
6 0 0 BPR6 0 R
5 0 0 BPR5 0 R
4 0 0 BPR4 0 R
3 HVEN 0 BPR3 0 R
2 MASS 0 BPR2 0 R
1 ERASE 0 BPR1 0 R
Bit 0 PGM 0 BPR0 0 R
$FE09
$FE0A
Freescale Semiconductor, Inc...
$FE0B
Reserved Write: Reset: Read: Break Address High Write: Register (BRKH) Reset: Read: Break Address Low Write: Register (BRKL) Reset:
R
R
R
R
R
R
R
R
$FE0C
Bit 15 0 Bit 7 0 BRKE 0
14 0 6 0 BRKA 0
13 0 5 0 0 0
12 0 4 0 0 0
11 0 3 0 0 0
10 0 2 0 0 0
9 0 1 0 0 0
Bit 8 0 Bit 0 0 0 0
$FE0D
Break Status and Control Read: $FE0E Register Write: (BRKSCR) Reset: Read: COP Control Register Write: (COPCTL) Reset: U = Unaffected
Low byte of reset vector Clears COP counter (any value) Unaffected by reset X = Indeterminate = Unimplemented R = Reserved
$FFFF
Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 12)
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com
Technical Data 53
Freescale Semiconductor, Inc.
Memory Map
Table 2-1. Vector Addresses
Vector Priority Lowest Vector IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 IF6 IF5 IF4 IF3 IF2 IF1 -- -- Address $FFDE $FFDF $FFE0 $FFE1 $FFE2 $FFE3 $FFE4 $FFE5 $FFE6 $FFE7 $FFE8 $FFE9 $FFEA $FFEB $FFEC $FFED $FFEE $FFEF $FFF0 $FFF1 $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF Vector ADC Conversion Complete Vector (High) ADC Conversion Complete Vector (Low) Keyboard Vector (High) Keyboard Vector (Low) SCI Transmit Vector (High) SCI Transmit Vector (Low) SCI Receive Vector (High) SCI Receive Vector (Low) SCI Error Vector (High) SCI Error Vector (Low) TIM2 Overflow Vector (High) TIM2 Overflow Vector (Low) TIM2 Channel 0 and 1 Vector (High) TIM2 Channel 0 and 1 Vector (Low) TIM2 Channel 1 Vector (High) TIM2 Channel 1 Vector (Low) TIM2 Channel 0 Vector (High) TIM2 Channel 0 Vector (Low) TIM1 Overflow Vector (High) TIM1 Overflow Vector (Low) TIM1 Channel 0 and 1 Vector (High) TIM1 Channel 0 and 1 Vector (Low) TIM1 Channel 1 Vector (High) TIM1 Channel 1 Vector (Low) TIM1 Channel 0 Vector (High) TIM1 Channel 0 Vector (Low) IRQ Vector (High) IRQ Vector (Low) USB Vector (High) USB Vector (Low) SWI Vector (High) SWI Vector (Low) Reset Vector (High) Reset Vector (Low)
.
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Highest
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Section 3. Random-Access Memory (RAM)
3.1 Contents
3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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3.3
3.2 Introduction
This section describes the 384 bytes of RAM (random-access memory).
3.3 Functional Description
Addresses $0080 through $01FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64K-byte memory space.
NOTE:
For correct operation, the stack pointer must point only to RAM locations. Within page zero are 128 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF out of page zero, direct addressing mode instructions can efficiently access all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers.
NOTE:
For M6805 compatibility, the H register is not stacked.
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Random-Access Memory (RAM)
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls.
NOTE:
Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
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Section 4. FLASH Memory
4.1 Contents
4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 60 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 61 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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4.3 4.4 4.5 4.6 4.7
4.8 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.8.1 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . .64 4.9 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 4.9.1 Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.9.2 ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 4.9.3 PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.9.4 VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.2 Introduction
This section describes the operation of the embedded FLASH memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump.
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FLASH Memory
Addr.
Register Name Read: FLASH Control Register Write: (FLCR) Reset: Read: FLASH Block Protect Register Write: (FLBPR) Reset:
Bit 7 0
6 0
5 0
4 0
3 HVEN
2 MASS 0 BPR2 0
1 ERASE 0 BPR1 0
Bit 0 PGM 0 BPR0 0
$FE08
0 BPR7 0
0 BPR6 0
0 BPR5 0
0 BPR4 0
0 BPR3 0
$FE09
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= Unimplemented
Figure 4-1. FLASH I/O Register Summary
4.3 Functional Description
The FLASH memory consists of an array of 16,384 bytes for user memory plus a block of 48 bytes for user interrupt vectors. An erased bit reads as logic 1 and a programmed bit reads as a logic 0. The FLASH memory is block erasable. The minimum erase block size is 512 bytes. Program and erase operation operations are facilitated through control bits in FLASH Control Register (FLCR).The address ranges for the FLASH memory are shown as follows: * * $BA00-$F9FF (user memory, 16,384 bytes) $FFD0-$FFFF (user interrupt vectors, 48 bytes)
Programming tools are available from Motorola. Contact your local Motorola representative for more information.
NOTE:
A security feature prevents viewing of the FLASH contents.1
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users.
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FLASH Memory FLASH Control Register
4.4 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operation.
Address: $FE08 Bit 7 Read: Write: 0 6 0 5 0 4 0 HVEN MASS 0 ERASE 0 PGM 0 3 2 1 Bit 0
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Reset:
0
0
0
0
0
= Unimplemented
Figure 4-2. FLASH Control Register (FLCR) HVEN -- High Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM=1 or ERASE=1 and the sequence for erase or program/verify is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS -- Mass Erase Control Bit This read/write bit configures the memory for mass erase operation or block erase operation when the ERASE bit is set. 1 = Mass Erase operation selected 0 = Block Erase operation selected ERASE -- Erase Control Bit This read/write bit configures the memory for erase operation. This bit and the PGM bit should not be set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation not selected PGM -- Program Control Bit This read/write bit configures the memory for program operation. This bit and the ERASE bit should not be set to 1 at the same time. 1 = Program operation selected 0 = Program operation not selected
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FLASH Memory 4.5 FLASH Block Erase Operation
Use the following procedure to erase a block of FLASH memory. A block consists of 512 consecutive bytes starting from addresses $X000, $X200, $X400, $X600, $X800, $XA00, $XC00 or $XE00. The 48-byte user interrupt vectors area also forms a block. Any block within the 16K bytes user memory area ($BA00-$F9FF) can be erased alone.
NOTE:
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The 48-byte user interrupt vectors, $FFD0-$FFFF, cannot be erased by the block erase operation because of security reasons. Mass erase is required to erase this block. 1. Set the ERASE bit and clear the MASS bit in the FLASH control register. 2. Write any data to any FLASH address within the address range of the block to be erased. 3. Wait for a time, tnvs (5s). 4. Set the HVEN bit. 5. Wait for a time tErase (10ms). 6. Clear the ERASE bit. 7. Wait for a time, tnvh (5s). 8. Clear the HVEN bit. 9. After time, trcv (1s), the memory can be accessed in read mode again.
NOTE:
Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.
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FLASH Memory FLASH Mass Erase Operation
4.6 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Write any data to any FLASH address within the address range $FFD0-$FFFF. 3. Wait for a time, tnvs (5s).
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4. Set the HVEN bit. 5. Wait for a time tMErase (200ms). 6. Clear the ERASE bit. 7. Wait for a time, tnvhl (100s). 8. Clear the HVEN bit. 9. After time, trcv (1s), the memory can be accessed in read mode again.
NOTE:
Programming and erasing of FLASH locations cannot be performed by executing code from the FLASH memory; the code must be executed from RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.
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FLASH Memory 4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80 or $XXC0. The procedure for programming a row of the FLASH memory is outlined below: 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming.
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2. Write any data to any FLASH address within the address range of the row to be programmed. 3. Wait for a time, tnvs (5s). 4. Set the HVEN bit. 5. Wait for a time, tpgs (10s). 6. Write data to the byte being programmed. 7. Wait for time, tProg (30s). 8. Repeat steps 6 and 7 until all the bytes within the row are programmed. 9. Clear the PGM bit. 10. Wait for time, tnvh (5s). 11. Clear the HVEN bit. 12. After time, trcv (1s), the memory can be accessed in read mode again. This program sequence is repeated throughout the memory until all data is programmed.
NOTE:
Programming and erasing of FLASH locations cannot be performed by executing code from the FLASH memory; the code must be executed from RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. Do not exceed tProg maximum. See 20.14 FLASH Memory Characteristics. Figure 4-3 shows a flowchart representation for programming the FLASH memory.
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FLASH Memory FLASH Program Operation
1
Set PGM bit
Algorithm for programming a row (64 bytes) of FLASH memory
2
Write any data to any FLASH address within the row address range desired
3
Wait for a time, tnvs
4
Set HVEN bit
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5
Wait for a time, tpgs
6
Write data to the FLASH address to be programmed
7
Wait for a time, tProg
Completed programming this row? N
9
Y
NOTE: The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH address programmed to clearing PGM bit (step 6 to step 9) must not exceed the maximum programming time, tProg max. This row program algorithm assumes the row/s to be programmed are initially erased.
Clear PGM bit
10
Wait for a time, tnvh
11
Clear HVEN bit
12
Wait for a time, trcv
End of Programming
Figure 4-3. FLASH Programming Flowchart
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FLASH Memory 4.8 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH Block Protect Register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations.
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NOTE:
When the FLBPR is cleared (all 0's), the entire FLASH memory is protected from being programmed and erased. When all the bits are set, the entire FLASH memory is accessible for program and erase.
4.8.1 FLASH Block Protect Register The FLASH block protect register is implemented as an 8-bit I/O register. The 7 bits of the 8-bit content of this register determine the starting location of the protected range within the FLASH memory.
Address: $FE09 Bit 7 Read: BPR7 Write: Reset: 0 0 0 0 0 0 0 0 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 6 5 4 3 2 1 Bit 0
Figure 4-4. FLASH Block Protect Register (FLBPR) BPR[7:0] -- FLASH Block Protect Register Bit 7 to Bit 0 BPR[7:1] represent bits [15:9] of a 16-bit memory address; bits [8:0] are logic 0's.
16-bit memory address Start address of FLASH block protect BPR[7:1] 000000000
Figure 4-5. FLASH Block Protect Start Address
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FLASH Memory ROM-Resident Routines
BPR0 is used only for BPR[7:0] = $FF, for no block protection. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be X000, X200, X400, X600, X800, XA00, XC00, or XE00 within the FLASH memory. Examples of protect start address:
BPR[7:0] Start of Address of Protect Range The entire FLASH memory is protected. $BC00 (1011 1100 0000 0000) $BE00 (1011 1110 0000 0000) $C000 (1100 0000 0000 0000) $C200 (1100 0010 0000 0000)
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$00 to $BA $BC (1011 1100) $BE (1011 1110) $C0 (1100 0000) $C2 (1100 0010) and so on... $FE $FF
$FFD0-$FFFF (User vectors) The entire FLASH memory is not protected.
Note: The end address of the protected range is always $FFFF.
4.9 ROM-Resident Routines
ROM-resident routines can be called by a program running in user mode or in monitor mode (see Section 9. Monitor ROM (MON)) for FLASH programming, erasing, and verifying. The range of the FLASH memory must be unprotected (see 4.8 FLASH Protection) before calling the erase or programming routine. Table 4-1. ROM-Resident Routines
Routine Name VERIFY ERASE PROGRAM Call Address $FC03 $FC06 $FC09 Description FLASH verify routine FLASH mass or block erase routine FLASH program routine
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FLASH Memory
4.9.1 Variables The ROM-resident routines use three variables: CTRLBYT, CPUSPD and LADDR; and one data buffer. The minimum size of the data buffer is one byte and the maximum size is 64 bytes. CPUSPD must be set before calling the erase or programming routines, and should be set to four times the value of the CPU internal bus speed in MHz. For example: for CPU speed of 6MHz, CPUSPD should be set to 24.
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Table 4-2. Summary of FLASH Routine Variables
Variable CTRLBYT CPUSPD LADDR DATABUF Address $0088 $0089 $008A-$008B $0100-$013F Description Control byte for setting mass or block erase. Timing adjustment for different CPU speeds. Last FLASH address to be programmed. Data buffer for programming and verifying.
4.9.2 ERASE Routine The ERASE routine erases the entire or a block of FLASH memory. The routine does not check for a blank range before or after erase.
NOTE:
A block erase cannot be performed on the last block of FLASH memory (user vector at $FFD0)-$FFFF). Table 4-3. ERASE Routine
Routine Calling Address Stack Use ERASE $FC06 5 Bytes CPUSPD -- CPU speed HX -- Contains any address in the range to be erased CTRLBYT -- Mass or block erase Mass erase if bit 6 = 1 Block erase if bit 6 = 0
Input
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FLASH Memory ROM-Resident Routines
4.9.3 PROGRAM Routine The PROGRAM routine programs a range of addresses in FLASH memory, which does not have to be on page boundaries, either at the begin or end address. Table 4-4. PROGRAM Routine
Routine Calling Address PROGRAM $FC09 7 Bytes CPUSPD -- HX -- LADDR -- DATABUF -- CPU speed FLASH start address to be programmed FLASH end address to be programmed Contains the data to be programmed
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Stack Use
Input
4.9.4 VERIFY Routine The VERIFY routine reads and verifies a range of FLASH memory. Table 4-5. VERIFY Routine
Routine Calling Address Stack Use Input VERIFY $FC03 6 Bytes HX -- FLASH start address to be verified LADDR -- FLASH end address to be verified DATABUF -- Contains the data to be verified C Bit -- C bit is set if verify passes DATABUF -- Contains the data in the range of the FLASH memory
Output
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FLASH Memory
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Section 5. Configuration Register (CONFIG)
5.1 Contents
5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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5.3 5.4
5.2 Introduction
This section describes the configuration register, CONFIG. The configuration register enables or disables these options: * * * * * * Low voltage inhibit (LVI) module control and voltage trip point selection USB reset Stop mode recovery time (2048 or 4096 OSCDCLK cycles) COP timeout period (218 - 24 or 213 - 24 OSCDCLK cycles) STOP instruction Computer operating properly module (COP)
5.3 Functional Description
The configuration register is used in the initialization of various options. The configuration register can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU, it is recommended that this register be written immediately after reset. The configuration register is located at $001F. The configuration register may be read at anytime.
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Configuration Register (CONFIG) 5.4 Configuration Register
Address: $001F Bit 7 Read: LVIDR Write: Reset: 0* 0* 0* 0* 0 0 0 0 LVI5OR3 URSTD LVID SSREC COPRS STOP COPD 6 5 4 3 2 1 Bit 0
* LVIDR, LVI5OR3, URSTD, and LVID bits are reset by POR (power-on reset) or LVI reset only.
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Figure 5-1. Configuration Register (CONFIG) LVIDR -- LVI Disable Bit for VREG LVIDR disables the LVI circuit for VREG. (See Section 18. LowVoltage Inhibit (LVI).) 1 = LVI circuit for VREG disabled 0 = LVI circuit for VREG enabled
NOTE:
There is no LVI circuit for VREGA. LVI5OR3 -- LVI Trip Point Voltage Select Bit for VDD LVI5OR3 selects the trip point voltage of the LVI circuit for VDD. (See Section 18. Low-Voltage Inhibit (LVI).) 1 = LVI trips at 3.3V 0 = LVI trips at 2.4V URSTD -- USB Reset Disable Bit URSTD disables the USB reset signal generating an internal reset to the CPU and internal registers. Instead, it will generate an interrupt request to the CPU. (See Section 11. Universal Serial Bus Module (USB).) 1 = USB reset generates a USB interrupt request to CPU 0 = USB reset generates a chip reset LVID -- LVI Disable Bit for VDD LVID disables the LVI circuit for VDD. (See Section 18. Low-Voltage Inhibit (LVI).) 1 = LVI circuit for VDD disabled 0 = LVI circuit for VDD enabled
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Configuration Register (CONFIG) Configuration Register
SSREC -- Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 2048 OSCDCLK cycles instead of a 4096 OSCDCLK cycle delay. 1 = Stop mode recovery after 2048 OSCDCLK cycles 0 = Stop mode recovery after 4096 OSCDCLK cycles
NOTE:
Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal oscillator, do not set the SSREC bit.
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COPRS -- COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS. (See Section 17. Computer Operating Properly (COP).) 1 = COP timeout period is 213 - 24 OSCDCLK cycles 0 = COP timeout period is 218 - 24 OSCDCLK cycles STOP -- STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD -- COP Disable Bit COPD disables the COP module. (See Section 17. Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled
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Configuration Register (CONFIG)
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Technical Data 72 Configuration Register (CONFIG) For More Information On This Product, Go to: www.freescale.com
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Technical Data -- MC68HC908JG16
Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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6.3
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .78 6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.7 6.8 6.9 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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Central Processor Unit (CPU) 6.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
6.3 Features
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Feature of the CPU include: * * * * * * * * * * * Object code fully upward-compatible with M68HC05 Family 16-bit stack pointer with stack manipulation instructions 16-Bit index register with X-register manipulation instructions 6-MHz CPU internal bus frequency 64-Kbyte program/data memory space 16 addressing modes Memory-to-memory data moves without using accumulator Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions Enhanced binary-coded decimal (BCD) data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64-Kbytes Low-power stop and wait modes
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Central Processor Unit (CPU) CPU Registers
6.4 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map.
7 15 H 15 X
0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC)
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15
7 0 V11HINZC
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
6.4.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7
Read: Write: Reset: Unaffected by reset
6
5
4
3
2
1
Bit 0
Figure 6-2. Accumulator (A)
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6.4.2 Index Register The 16-bit index register allows indexed addressing of a 64K-byte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
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Bit 15
Read: Write: Reset: 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 6-3. Index Register (H:X)
6.4.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
Bit 15
Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
Figure 6-4. Stack Pointer (SP)
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Central Processor Unit (CPU) CPU Registers
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.
6.4.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched.
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Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit 15
Read: Write: Reset: Loaded with Vector from $FFFE and $FFFF
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
Figure 6-5. Program Counter (PC)
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Central Processor Unit (CPU)
6.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register.
Bit 7
Read:
6 1 1
5 1 1
4 H X
3 I 1
2 N X
1 Z X
Bit 0 C X
V
Write:
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Reset:
X
X = Indeterminate
Figure 6-6. Condition Code Register (CCR) V -- Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H -- Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or addwith-carry (ADC) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4
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Central Processor Unit (CPU) CPU Registers
I -- Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled
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NOTE:
To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N -- Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z -- Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result
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C -- Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions -- such as bit test and branch, shift, and rotate -- also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7
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6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
6.6.1 Wait Mode The WAIT instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock.
*
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Central Processor Unit (CPU) CPU During Break Interrupts
6.6.2 Stop Mode The STOP instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock.
*
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After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
6.7 CPU During Break Interrupts
If the break module is enabled, a break interrupt causes the CPU to execute the software interrupt instruction (SWI) at the completion of the current CPU instruction. (See Section 19. Break Module (BRK).) The program counter vectors to $FFFC-$FFFD ($FEFC-$FEFD in monitor mode). A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.
6.8 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
6.9 Opcode Map
The opcode map is provided in Table 6-2.
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Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 1 of 8)
Cycles 2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4 Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP Operand ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff dd ff ff dd ff ff rr dd dd dd dd dd dd dd dd Address Mode Opcode A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4 38 48 58 68 78 9E68 37 47 57 67 77 9E67 24 11 13 15 17 19 1B 1D 1F Effect on CCR VH INZC
Operation
Description
Add with Carry
A (A) + (M) + (C)
IMM DIR EXT IX2 - IX1 IX SP1 SP2 IMM DIR EXT IX2 - IX1 IX SP1 SP2 - - - - - - IMM - - - - - - IMM IMM DIR EXT IX2 0--- IX1 IX SP1 SP2 DIR INH INH -- IX1 IX SP1 DIR INH INH -- IX1 IX SP1 - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) ------ DIR (b4) DIR (b5) DIR (b6) DIR (b7)
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ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel
Add without Carry
A (A) + (M)
Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X
SP (SP) + (16 M) H:X (H:X) + (16 M)
Logical AND
A (A) & (M)
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
Arithmetic Shift Right
b7 b0
C
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? (C) = 0
BCLR n, opr
Clear Bit n in M
Mn 0
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Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary (Sheet 2 of 8)
Cycles 3 3 3 3 3 3 3 3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 3 3 3 Source Form BCS rel BEQ rel BGE opr BGT opr Operand rr rr rr rr rr rr rr rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr rr rr rr Address Mode Opcode 25 27 90 92 28 29 22 24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D 26 2A 20 Effect on CCR VH INZC Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1 PC (PC) + 2 + rel ? (N V) = 0
PC (PC) + 2 + rel ? (Z) | (N V) = 0
Operation
Description
- - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL IMM DIR EXT IX2 0--- IX1 IX SP1 SP2 - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL
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BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
Bit Test
(A) & (M)
Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? (Z) | (N V) = 1
PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel
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Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 3 of 8)
Cycles 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 5 4 4 5 4 6 1 2 dd 3 1 1 1 3 2 4 Source Form Operand dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd rr dd rr ii rr ii rr ff rr rr ff rr ff ff Address Mode Opcode 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E AD 31 41 51 61 71 9E61 98 9A 3F 4F 5F 8C 6F 7F 9E6F Effect on CCR VH INZC
Operation
Description
BRCLR n,opr,rel Branch if Bit n in M Clear
PC (PC) + 3 + rel ? (Mn) = 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ----- DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) ----- DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ------ DIR (b4) DIR (b5) DIR (b6) DIR (b7)
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BRN rel
Branch Never
PC (PC) + 2
BRSET n,opr,rel Branch if Bit n in M Set
PC (PC) + 3 + rel ? (Mn) = 1
BSET n,opr
Set Bit n in M
Mn 1
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel
- - - - - - REL
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP Clear Carry Bit Clear Interrupt Mask
PC (PC) + 3 + rel ? (A) - (M) = $00 DIR PC (PC) + 3 + rel ? (A) - (M) = $00 IMM PC (PC) + 3 + rel ? (X) - (M) = $00 IMM ------ IX1+ PC (PC) + 3 + rel ? (A) - (M) = $00 IX+ PC (PC) + 2 + rel ? (A) - (M) = $00 SP1 PC (PC) + 4 + rel ? (A) - (M) = $00 C0 I0 M $00 A $00 X $00 H $00 M $00 M $00 M $00 - - - - - 0 INH - - 0 - - - INH DIR INH INH 0 - - 0 1 - INH IX1 IX SP1
Clear
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Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary (Sheet 4 of 8)
Cycles 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4 2 3 4 4 3 2 4 5 2 dd rr rr rr ff rr rr ff rr dd 5 3 3 5 4 6 4 1 1 4 3 5 7 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 Source Form CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Operand ii dd hh ll ee ff ff ff ee ff dd ff ff ii ii+1 dd ii dd hh ll ee ff ff ff ee ff ff ff Address Mode Opcode A1 B1 C1 D1 E1 F1 9EE1 9ED1 33 43 53 63 73 9E63 65 75 A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B 3A 4A 5A 6A 7A 9E6A 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8 Effect on CCR VH INZC
Operation
Description
Compare A with M
(A) - (M)
IMM DIR EXT IX2 -- IX1 IX SP1 SP2 DIR INH INH 0--1 IX1 IX SP1 -- IMM DIR
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COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA
Complement (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) (H:X) - (M:M + 1)
Compare H:X with M
Compare X with M
(X) - (M)
IMM DIR EXT IX2 -- IX1 IX SP1 SP2 U - - INH DIR INH - - - - - - INH IX1 IX SP1 DIR INH INH --- IX1 IX SP1 - - - - INH IMM DIR EXT IX2 0--- IX1 IX SP1 SP2
Decimal Adjust A
(A)10
A (A) - 1 or M (M) - 1 or X (X) - 1
DBNZ opr,rel DBNZA rel Decrement and Branch if Not Zero DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP
PC (PC) + 3 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 3 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 4 + rel ? (result) 0 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder
Decrement
Divide
Exclusive OR M with A
A (A M)
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Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 5 of 8)
Cycles 4 1 1 4 3 5 2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5 3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 Source Form INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP Operand dd ff ff dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff ii jj dd ii dd hh ll ee ff ff ff ee ff dd ff ff dd ff ff Address Mode Opcode 3C 4C 5C 6C 7C 9E6C BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 45 55 AE BE CE DE EE FE 9EEE 9EDE 38 48 58 68 78 9E68 34 44 54 64 74 9E64 Effect on CCR VH INZC M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1
Operation
Description
Increment
DIR INH INH --- IX1 IX SP1 DIR EXT - - - - - - IX2 IX1 IX DIR EXT - - - - - - IX2 IX1 IX IMM DIR EXT IX2 0--- IX1 IX SP1 SP2 0--- IMM DIR
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Jump
PC Jump Address
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address
Load A from M
A (M)
Load H:X from M
H:X (M:M + 1)
Load X from M
X (M)
IMM DIR EXT IX2 0--- IX1 IX SP1 SP2 DIR INH INH -- IX1 IX SP1 DIR INH INH --0 IX1 IX SP1
Logical Shift Left (Same as ASL)
C b7 b0
0
Logical Shift Right
0 b7 b0
C
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Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary (Sheet 6 of 8)
Cycles 5 4 4 4 5 dd 4 1 1 4 3 5 1 3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 2 2 2 2 2 2 dd 4 1 1 4 3 5 4 1 1 4 3 5 1 Source Form MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX PULA PULH PULX ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP Operand dd dd dd ii dd dd ff ff ff ff dd ff ff Address Mode Opcode 4E 5E 6E 7E 42 30 40 50 60 70 9E60 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 86 8A 88 39 49 59 69 79 9E69 36 46 56 66 76 9E66 9C Effect on CCR VH INZC (M)Destination (M)Source Move H:X (H:X) + 1 (IX+D, DIX+) Unsigned multiply X:A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4])
Operation
Description
DD DIX+ 0--- IMD IX+D - 0 - - - 0 INH DIR INH INH -- IX1 IX SP1 - - - - - - INH - - - - - - INH IMM DIR EXT IX2 0--- IX1 IX SP1 SP2 - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH DIR INH INH -- IX1 IX SP1 DIR INH INH -- IX1 IX SP1 - - - - - - INH
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Negate (Two's Complement)
No Operation Nibble Swap A
Inclusive OR A and M
A (A) | (M)
Push A onto Stack Push H onto Stack Push X onto Stack Pull A from Stack Pull H from Stack Pull X from Stack
Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1 SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X)
Rotate Left through Carry
C b7 b0
Rotate Right through Carry
b7 b0
C
Reset Stack Pointer
SP $FF
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Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 7 of 8)
Cycles 7 4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 1 2 dd hh ll ee ff ff ff ee ff dd 3 4 4 3 2 4 5 4 1 dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 Source Form Operand Address Mode Opcode 80 81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0 Effect on CCR VH INZC SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL)
Operation
Description
RTI
Return from Interrupt
INH
RTS
Return from Subroutine
- - - - - - INH IMM DIR EXT IX2 -- IX1 IX SP1 SP2 - - - - - 1 INH - - 1 - - - INH DIR EXT IX2 0 - - - IX1 IX SP1 SP2 0 - - - DIR - - 0 - - - INH DIR EXT IX2 0 - - - IX1 IX SP1 SP2 IMM DIR EXT IX2 -- IX1 IX SP1 SP2
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SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Subtract with Carry
A (A) - (M) - (C)
Set Carry Bit Set Interrupt Mask
C1 I1
Store A in M
M (A)
Store H:X in M Enable IRQ Pin; Stop Oscillator
(M:M + 1) (H:X) I 0; Stop Oscillator
Store X in M
M (X)
Subtract
A (A) - (M)
Technical Data 88 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary (Sheet 8 of 8)
Cycles 9 2 1 1 dd 3 1 1 3 2 4 2 1 2 Source Form Operand ff ff Address Mode Opcode 83 84 97 85 3D 4D 5D 6D 7D 9E6D 95 9F 94 Effect on CCR VH INZC PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR)
Operation
Description
SWI
Software Interrupt
- - 1 - - - INH
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TAP TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N
Transfer A to CCR Transfer A to X Transfer CCR to A
INH - - - - - - INH - - - - - - INH DIR INH INH 0--- IX1 IX SP1 - - - - - - INH - - - - - - INH - - - - - - INH n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & |
Test for Negative or Zero
(A) - $00 or (X) - $00 or (M) - $00
Transfer SP to H:X Transfer X to A Transfer H:X to SP
H:X (SP) + 1 A (X) (SP) (H:X) - 1
Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit
() -( ) #
? : --
Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com
Technical Data 89
Freescale Semiconductor, Inc...
Table 6-2. Opcode Map
Branch REL DIR 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE INH SP1 IX IMM DIR EXT IX1 SP1 IX F 2 Read-Modify-Write INH IX1 Control INH INH Register/Memory IX2 SP2
Technical Data
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
MSB LSB
Central Processor Unit (CPU)
90
4 4 4 4 4 4 4 4 4 4 4 4 2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM 5 SUB SP2 5 CMP SP2 5 SBC SP2 5 CPX SP2 5 AND SP2 5 BIT SP2 5 LDA SP2 5 STA SP2 5 EOR SP2 5 ADC SP2 5 ORA SP2 5 ADD SP2 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1 4 4 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL 4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1 5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX 7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH 3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR 4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT 4 SUB IX2 4 CMP IX2 4 SBC IX2 4 CPX IX2 4 AND IX2 4 BIT IX2 4 LDA IX2 4 STA IX2 4 EOR IX2 4 ADC IX2 4 ORA IX2 4 ADD IX2 4 JMP IX2 6 JSR IX2 4 LDX IX2 4 STX IX2 3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX SP2 2 IX1 5 3 STX STX SP2 2 IX1 2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX 0 Low Byte of Opcode in Hexadecimal 0 SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment High Byte of Opcode in Hexadecimal 5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode
Bit Manipulation DIR DIR
MSB
0
1
LSB
0
1
2
3
4
5
6
7
8
9
A
B
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Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com
C
D
E
F
5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR
4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR
MC68HC908JG16 -- Rev. 1.0
Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset Direct-Direct IMD Immediate-Direct Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions
INH IMM DIR EXT DD IX+D
MOTOROLA
Freescale Semiconductor, Inc.
Technical Data -- MC68HC908JG16
Section 7. Oscillator (OSC)
7.1 Contents
7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . . 92
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7.3
7.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . 93 7.4.2 Crystal Amplifier Output Pin (OSC1) . . . . . . . . . . . . . . . . . . 93 7.4.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . 93 7.4.4 Crystal Output Frequency Signal (OSCXCLK). . . . . . . . . . . 93 7.4.5 Clock Doubler Out (OSCDCLK) . . . . . . . . . . . . . . . . . . . . . . 93 7.4.6 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.6 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.2 Introduction
The oscillator circuit is designed for use with crystals or ceramic resonators. The oscillator circuit generates the crystal clock signal, OSCXCLK, and passes through a clock doubler to produce OSCDCLK. This clock doubler clock is further divided by two before being passed on to the system integration module (SIM) for bus clock generation. Figure 7-1 shows the structure of the oscillator. The oscillator requires various external components. The MC68HC908JG16 operates from a nominal 12MHz crystal, providing a 6MHz internal bus clock. The 12MHz clock is required for various modules, such as the USB and SCI. The clock doubler clock, OSCDCLK, is used as the base clock for the COP module.
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Oscillator (OSC) For More Information On This Product, Go to: www.freescale.com Technical Data 91
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Oscillator (OSC) 7.3 Oscillator External Connections
In its typical configuration, the oscillator requires five external components. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 7-1. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: * Crystal, X1 (nominally 12MHz) Fixed capacitor, C1 Tuning capacitor, C2 (can also be a fixed capacitor) Feedback resistor, RB Series resistor, RS (not required for 12MHz)
TO COP, SCI TO SIM
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* * * *
FROM SIM
OSCXCLK SIMOSCEN
CLOCK DOUBLER
OSCDCLK
/2
OSCOUT
/2 MCU OSC1 RB OSC2
TO USB
RS* X1 * RS can be 0 (shorted) when used with higher frequency crystals. Refer to manufacturer's data.
C1
12 MHz
C2
Figure 7-1. Oscillator External Connections The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high-frequency crystals. Refer to the crystal manufacturer's data for more information.
Technical Data 92 Oscillator (OSC) For More Information On This Product, Go to: www.freescale.com MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Oscillator (OSC) I/O Signals
7.4 I/O Signals
The following paragraphs describe the oscillator input/output (I/O) signals.
7.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier.
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7.4.2 Crystal Amplifier Output Pin (OSC1) The OSC2 pin is the output of the crystal oscillator inverting amplifier.
7.4.3 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator.
7.4.4 Crystal Output Frequency Signal (OSCXCLK) OSCXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 7-1 shows only the logical relation of OSCXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of OSCXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of OSCXCLK can be unstable at startup.
7.4.5 Clock Doubler Out (OSCDCLK) OSCDCLK is the clock doubler output signal. It runs at twice the speed of the crystal (fXCLK) and comes from the clock doubler circuit.
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Technical Data 93
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Oscillator (OSC)
7.4.6 Oscillator Out (OSCOUT) OSCOUT is the divide-by-two signal after the clock doubler circuit. It runs at the same speed as OSCXCLK, at crystal frequency (fXCLK). This signal goes to the SIM, which generates the MCU clocks. OSCOUT will be divided-by-two again in the SIM and results in the internal bus frequency being one half of the crystal frequency.
7.5 Low-Power Modes
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The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes.
7.5.1 Wait Mode The WAIT instruction has no effect on the oscillator logic. OSCXCLK continues to drive to the MCU.
7.5.2 Stop Mode The STOP instruction disables the OSCXCLK output.
7.6 Oscillator During Break Mode
The oscillator continues to drive OSCXCLK when the chip enters the break state.
Technical Data 94 Oscillator (OSC) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Technical Data -- MC68HC908JG16
Section 8. System Integration Module (SIM)
8.1 Contents
8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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8.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 98 8.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . 99 8.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 99 8.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 99 8.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 101 8.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . 103 8.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . 104 8.4.2.6 Universal Serial Bus (USB) Reset . . . . . . . . . . . . . . . . . 104 8.4.2.7 Registers Values After Different Resets. . . . . . . . . . . . . 104 8.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 105 8.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 106 8.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .106 8.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 110 8.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
MC68HC908JG16 -- Rev. 1.0 MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Technical Data 95
Freescale Semiconductor, Inc.
System Integration Module (SIM)
8.6.4 8.6.5 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 113
8.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 8.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.8.1 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . 117 8.8.2 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . 118 8.8.3 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . .119
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8.2 Introduction
This section describes the system integration module (SIM). Together with the CPU, the SIM controls all MCU activities. The SIM is a system state controller that coordinates CPU and exception timing. A block diagram of the SIM is shown in Figure 8-1. Figure 8-2 is a summary of the SIM I/O registers. The SIM is responsible for: * Bus clock generation and control for CPU and peripherals - Stop/wait/reset/break entry and recovery - Internal clock control * * Master reset control, including power-on reset (POR) and COP timeout Interrupt control: - Acknowledge timing - Arbitration control timing - Vector address generation * * CPU enable/disable timing Modular architecture expandable to 128 interrupt sources
Table 8-1 shows the internal signal names used in this section.
Technical Data 96 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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System Integration Module (SIM) Introduction
MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK
OSCDCLK (FROM OSC) OSCOUT (FROM OSC) /2 VDD CLOCK CONTROL CLOCK GENERATORS INTERNAL CLOCKS
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INTERNAL PULL-UP
RESET PIN LOGIC
POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL
ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) LVI RESET (FROM LVI MODULE) USB RESET (FROM USB MODULE)
RESET
INTERRUPT CONTROL AND PRIORITY DECODE
INTERRUPT SOURCES CPU INTERFACE
Figure 8-1. SIM Block Diagram Table 8-1. SIM Module Signal Name Conventions
Signal Name OSCDCLK OSCOUT IAB IDB PORRST IRST R/W Description Clock doubler output which has twice the frequency of OSC1 from the oscillator The OSCDCLK frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks. (Bus clock = OSCDCLK / 4 = OSCXCLK / 2) Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal
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Technical Data 97
Freescale Semiconductor, Inc.
System Integration Module (SIM)
Addr.
Register Name
Bit 7 R
6 R
5 R
4 R
3 R
2 R
1 SBSW See note 0
Bit 0 R
Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Note: Writing a logic 0 clears SBSW. Read: SIM Reset Status Register $FE01 Write: (SRSR) POR:
POR
PIN
COP
ILOP
ILAD
USB
LVI
0
1 BCFE 0 IF6 R 0 IF14 R 0 0 R 0
0 R
0 R
0 R
0 R
0 R
0 R
0 R
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$FE03
Read: SIM Break Flag Control Register Write: (SBFCR) Reset:
Read: Interrupt Status Register 1 $FE04 Write: (INT1) Reset: Read: Interrupt Status Register 2 $FE05 Write: (INT2) Reset: Read: Interrupt Status Register 3 $FE06 Write: (INT3) Reset:
IF5 R 0 IF13 R 0 0 R 0
IF4 R 0 IF12 R 0 0 R 0
IF3 R 0 IF11 R 0 0 R 0
IF2 R 0 IF10 R 0 0 R 0
IF1 R 0 IF9 R 0 0 R 0
0 R 0 IF8 R 0 0 R 0
0 R 0 IF7 R 0 IF15 R 0
Figure 8-2. SIM I/O Register Summary
8.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, OSCOUT, as shown in Figure 8-3.
OSCDCLK FROM OSC OSCOUT
SIM COUNTER /2 BUS CLOCK GENERATORS
SIM
Figure 8-3. SIM Clock Signals
Technical Data 98 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
System Integration Module (SIM) Reset and System Initialization
8.3.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency divided by two. 8.3.2 Clock Startup from POR or LVI Reset When the power-on reset (POR) module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 OSCDCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. 8.3.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt, break, or reset, the SIM allows OSCDCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 2048 OSCDCLK cycles. (See 8.7.2 Stop Mode.) In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
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8.4 Reset and System Initialization
The MCU has the following reset sources: * * * * * * *
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Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Illegal opcode Illegal address Universal serial bus module (USB) Low-voltage inhibit module (LVI)
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System Integration Module (SIM)
All of these resets produce the vector $FFFE-FFFF ($FEFE-FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 8.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 8.8 SIM Registers.)
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8.4.1 External Pin Reset The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 OSCDCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 8-2 for details. Figure 8-4 shows the relative timing. Table 8-2. PIN Bit Set Timing
Reset Type POR/LVI All others Number of Cycles Required to Set PIN 4163 (4096 + 64 + 3) 67 (64 + 3)
OSCOUT
RST
IAB
PC
VECT H VECT L
Figure 8-4. External Reset Timing
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System Integration Module (SIM) Reset and System Initialization
8.4.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 OSCDCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles. (See Figure 8-5.) An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, the USB module or POR. (See Figure 8-6 . Sources of Internal Reset.)
NOTE:
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For LVI or POR resets, the SIM cycles through 4096 OSCDCLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 8-5.
IRST
RST
RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES
OSCDCLK
IAB
VECTOR HIGH
Figure 8-5. Internal Reset Timing The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR LVI USB
INTERNAL RESET
Figure 8-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU.
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System Integration Module (SIM)
8.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 OSCDCLK cycles. Sixty-four OSCDCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur:
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* * * * * *
A POR pulse is generated. The internal reset signal is asserted. The SIM enables the oscillator to drive OSCDCLK. Internal clocks to the CPU and modules are held inactive for 4096 OSCDCLK cycles to allow stabilization of the oscillator. The RST pin is driven low during the oscillator stabilization time. The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared.
OSC1
PORRST 4096 CYCLES OSCDCLK 32 CYCLES 32 CYCLES
OSCOUT
RST
IAB
$FFFE
$FFFF
Figure 8-7. POR Recovery
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System Integration Module (SIM) Reset and System Initialization
8.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module timeout, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and stages 12 through 5 of the SIM counter. The SIM counter output, which occurs at least every 212 - 24 OSCDCLK cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. The COP module is disabled if the RST pin or the IRQ pin is held at VTST while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VTST on the RST pin disables the COP module. 8.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 8.4.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources.
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System Integration Module (SIM)
8.4.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD or VREG voltage falls to the LVI reset voltage, VTRIP. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 OSCDCLK cycles. Sixty-four OSCDCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources.
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8.4.2.6 Universal Serial Bus (USB) Reset The USB module will detect a reset signaled on the bus by the presence of an extended SE0 at the USB data pins of a device. The MCU seeing a single-ended 0 on its USB data inputs for more than 2.5s treats that signal as a reset. After the reset is removed, the device will be in the attached, but not yet addressed or configured, state (refer to Section 9.1 USB Devices of the Universal Serial Bus Specification Rev. 2.0). The device must be able to accept the device address via a SET_ADDRESS command (refer to Section 9.4 of the Universal Serial Bus Specification Rev. 2.0) no later than 10ms after the reset is removed. USB reset can be disabled to generate an internal reset. It can be configured to generate IRQ interrupt. (See Section 5. Configuration Register (CONFIG).)
NOTE:
USB reset is disabled when the USB module is disabled by clearing the USBEN bit of the USB address register (UADDR).
8.4.2.7 Registers Values After Different Resets Some registers are reset by POR or LVI reset only. Table 8-3 shows the registers or register bits which are unaffected by normal resets.
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System Integration Module (SIM) SIM Counter
Table 8-3. Registers not Affected by Normal Reset
Bits LVIDR, LVI5OR3, URSTD, LVID USBEN PULLEN All Registers After Reset (except POR or LVI) Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected After POR or LVI
CONFIG UADDR UCR3 USR0, USR1 UE0D0-UE0D7 UE1D0-UE1D7 UE2D0-UE2D7 PTA, PTB, PTC, PTD, and PTE DDRA
0 0 0 Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate 0
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All All All All DDRA7
8.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP module. The SIM counter is clocked by the falling edge of OSCDCLK.
8.5.1 SIM Counter During Power-On Reset The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine.
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8.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the configuration register (CONFIG). If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 OSCDCLK cycles down to 2048 OSCDCLK cycles. This is ideal for applications using canned oscillators that do not require long startup times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared in the configuration register (CONFIG).
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8.5.3 SIM Counter and Reset States External reset has no effect on the SIM counter. (See 8.7.2 Stop Mode for details.) The SIM counter is free-running after all reset states. (See 8.4.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.)
8.6 Exception Control
Normal, sequential program execution can be changed in three different ways: * Interrupts - Maskable hardware CPU interrupts - Non-maskable software interrupt instruction (SWI) * * Reset Break interrupts
8.6.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 8-8 flow charts the handling of system interrupts.
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System Integration Module (SIM) Exception Control
FROM RESET
BREAK INTERRUPT? I BIT SET? NO
YES
YES
I BIT SET?
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NO
USB INTERRUPT? NO
YES
IRQ INTERRUPT? NO (As many interrupts as exist on chip)
YES
STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT INSTRUCTION.
SWI INSTRUCTION? NO
YES
RTI INSTRUCTION? NO
YES
UNSTACK CPU REGISTERS.
EXECUTE INSTRUCTION.
Figure 8-8. Interrupt Processing
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System Integration Module (SIM)
Interrupts are latched and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced or the I bit is cleared. At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 8-9 shows interrupt entry timing. Figure 8-10 shows interrupt recovery timing.
MODULE INTERRUPT I BIT
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IAB
DUMMY
SP
SP - 1
SP - 2
SP - 3
SP - 4
VECT H
VECT L
START ADDR
IDB
DUMMY
PC - 1[7:0] PC - 1[15:8]
X
A
CCR
V DATA H
V DATA L
OPCODE
R/W
Figure 8-9. Interrupt Entry
MODULE INTERRUPT I BIT
IAB
SP - 4
SP - 3
SP - 2
SP - 1
SP
PC
PC + 1
IDB
CCR
A
X
PC - 1[15:8] PC - 1 [7:0] OPCODE
OPERAND
R/W
Figure 8-10. Interrupt Recovery
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System Integration Module (SIM) Exception Control
8.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed.
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If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 8-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
CLI LDA #$FF BACKGROUND ROUTINE
INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 8-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine.
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8.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register.
NOTE:
A software interrupt pushes PC onto the stack. A software interrupt does not push PC-1, as a hardware interrupt does.
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8.6.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 8-4 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. 8.6.2.1 Interrupt Status Register 1
Address: $FE04 Bit 7 Read: Write: Reset: IF6 R 0 R 6 IF5 R 0 = Reserved 5 IF4 R 0 4 IF3 R 0 3 IF2 R 0 2 IF1 R 0 1 0 R 0 Bit 0 0 R 0
Figure 8-12. Interrupt Status Register 1 (INT1) IF6-IF1 -- Interrupt Flags 6-1 These flags indicate the presence of interrupt requests from the sources shown in Table 8-4. 1 = Interrupt request present 0 = No interrupt request present Bit 1 and Bit 0 -- Always read 0
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Table 8-4. Interrupt Sources
Source Reset SWI instruction USB reset interrupt USB endpoint 0 transmit USB endpoint 0 receive USB endpoint 1 transmit Flags None None RSTF TXD0F RXD0F TXD1F TXD2F RXD2F EOPF RESUMF IRQF, PTE4IF CH0F CH1F CH0F & CH1F TOF CH0F CH1F CH0F & CH1F TOF OR NF FE PE SCRF IDLE SCTE TC KEYF COCO Mask(1) None None URSTD TXD0IE RXD0IE TXD1IE TXD2IE RXD2IE EOPIE -- IMASK CH0IE CH1IE CH01IE TOIE CH0IE CH1IE CH01IE TOIE ORIE NEIE FEIE PEIE SCRIE ILIE SCTIE TCIE IMASKK AIEN IF12 12 $FFE4-$FFE5 IF11 11 $FFE6-$FFE7 IF2 IF3 IF4 IF5 IF6 IF7 IF8 IF9 IF10 2 3 4 5 6 7 8 9 10 $FFF8-$FFF9 $FFF6-$FFF7 $FFF4-$FFF5 $FFF2-$FFF3 $FFF0-$FFF1 $FFEE-$FFEF $FFEC-$FFED $FFEA-$FFEB $FFE8-$FFE9 IF1 1 $FFFA-$FFFB INT Register Flag None None Priority(2) 0 0 Vector Address $FFFE-$FFFF $FFFC-$FFFD
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USB endpoint 2 transmit USB endpoint 2 receive USB end of packet USB resume interrupt IRQ interrupt (IRQ, PTE4) TIM 1 channel 0 TIM 1 channel 1 TIM 1 channel 0 & 1 TIM 1 overflow TIM 2 channel 0 TIM 2 channel 1 TIM 2 channel 0 & 1 TIM 2 overflow SCI receiver overrun SCI noise fag SCI framing error SCI parity error SCI receiver full SCI input idle SCI transmitter empty SCI transmission complete Keyboard interrupt ADC conversion complete
IF13 IF14 IF15
13 14 15
$FFE2-$FFE3 $FFE0-$FFE1 $FFDE-$FFDF
Notes: 1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction. 2. Highest priority = 0.
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8.6.2.2 Interrupt Status Register 2
Address: $FE05 Bit 7 Read: Write: Reset: IF14 R 0 R 6 IF13 R 0 = Reserved 5 IF12 R 0 4 IF11 R 0 3 IF10 R 0 2 IF9 R 0 1 IF8 R 0 Bit 0 IF7 R 0
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Figure 8-13. Interrupt Status Register 2 (INT2) IF14-IF7 -- Interrupt Flags 14-7 These flags indicate the presence of interrupt requests from the sources shown in Table 8-4. 1 = Interrupt request present 0 = No interrupt request present 8.6.2.3 Interrupt Status Register 3
Address: $FE06 Bit 7 Read: Write: Reset: 0 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 0 R 0 2 0 R 0 1 0 R 0 Bit 0 IF15 R 0
Figure 8-14. Interrupt Status Register 3 (INT3) IF15 -- Interrupt Flag 15 This flag indicates the presence of interrupt requests from the source shown in Table 8-4. 1 = Interrupt request present 0 = No interrupt request present Bit 7 to Bit 1 -- Always read 0
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8.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated.
8.6.4 Break Interrupts The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. (See Section 19. Break Module (BRK).) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.
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8.6.5 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the break flag control register (BFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a 2-step clearing mechanism -- for example, a read of one register followed by the read or write of another -- are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.
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System Integration Module (SIM) 8.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-powerconsumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described here. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur.
8.7.1 Wait Mode
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In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 8-15 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the configuration register (CONFIG) is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction
Figure 8-15. Wait Mode Entry Timing Figure 8-16 and Figure 8-17 show the timing for WAIT recovery.
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System Integration Module (SIM) Low-Power Modes
IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB
$A6
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin or CPU interrupt or break interrupt
Figure 8-16. Wait Recovery from Interrupt or Break
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32 CYCLES IAB $6E0B
32 CYCLES RST VCT H RST VCT L
IDB
$A6
$A6
$A6
RST
OSCDCLK
Figure 8-17. Wait Recovery from Internal Reset
8.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the oscillator signals (OSCOUT and OSCDCLK) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register (CONFIG). If SSREC is set, stop recovery is reduced from the normal delay of 4096 OSCDCLK cycles down to 2048. This is ideal for applications using canned oscillators that do not require long startup times from stop mode.
NOTE:
External crystal applications should use the full stop recovery time by clearing the SSREC bit.
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System Integration Module (SIM)
A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status register (SBSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 8-18 shows stop mode entry timing.
NOTE:
To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
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CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction
Figure 8-18. Stop Mode Entry Timing
STOP RECOVERY PERIOD OSCDCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP - 1
SP - 2
SP - 3
Figure 8-19. Stop Mode Recovery from Interrupt or Break
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System Integration Module (SIM) SIM Registers
8.8 SIM Registers
The SIM has three memory mapped registers. * * * SIM break status register (SBSR) SIM reset status register (SRSR) SIM break flag control register (SBFCR)
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8.8.1 SIM Break Status Register (SBSR) The SIM break status register contains a flag to indicate that a break caused an exit from stop or wait mode.
Address: $FE00 Bit 7 Read: R Write: Reset: Note 1. Writing a logic 0 clears SBSW. R = Reserved R R R R R Note 1 0 6 5 4 3 2 1 SBSW R Bit 0
Figure 8-20. SIM Break Status Register (SBSR) SBSW -- SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this. Writing 0 to the SBSW bit clears it.
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System Integration Module (SIM)
; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the break ; service routine software. HIBYTE LOBYTE ; EQU EQU 5 6
If not SBSW, do RTI BRCLR TST SBSW,SBSR, RETURN LOBYTE,SP DOLO HIBYTE,SP LOBYTE,SP ; See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ;Point to WAIT/STOP opcode. ;Restore H register.
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BNE DEC DOLO RETURN DEC PULH RTI
8.8.2 SIM Reset Status Register (SRSR) This register contains seven flags that show the source of the last reset. All flag bits are cleared automatically following a read of the register. The register is initialized on power-up as shown with the POR bit set and all other bits cleared. However, during a POR or any other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32 OSCDCLK cycles later. If the pin is not above a VIH at that time, then the PIN bit in the SRSR may be set in addition to whatever other bits are set.
Address: $FE01 Bit 7 Read: Write: POR: 1 0 0 0 0 0 0 0 POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 USB 1 LVI Bit 0 0
= Unimplemented
Figure 8-21. SIM Reset Status Register (SRSR) POR -- Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR
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System Integration Module (SIM) SIM Registers
PIN -- External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP -- Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP -- Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD -- Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR USB -- Universal Serial Bus Reset Bit 1 = Last reset caused by the USB module 0 = POR or read of SRSR LVI -- Low Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR
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8.8.3 SIM Break Flag Control Register (SBFCR) The SIM break flag control register contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: $FE03 Bit 7 Read: BCFE Write: Reset: 0 R
= Reserved
6 R
5 R
4 R
3 R
2 R
1 R
Bit 0 R
Figure 8-22. SIM Break Flag Control Register (SBFCR)
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System Integration Module (SIM)
BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
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Technical Data 120 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Technical Data -- MC68HC908JG16
Section 9. Monitor ROM (MON)
9.1 Contents
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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9.3
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 9.4.3 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 9.4.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.5.1 Extended Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.2 Introduction
This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with host computer. This mode is also used for programming and erasing of FLASH memory in the MCU. Monitor mode entry can be achieved without use of the higher voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
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Monitor ROM (MON) 9.3 Features
Features of the monitor ROM include the following: * * * Normal user-mode pin functionality One pin dedicated to serial communication between monitor ROM and host computer Standard mark/space non-return-to-zero (NRZ) communication with host computer Execution of code in RAM or FLASH FLASH memory security feature1 FLASH memory programming interface 1,472 bytes monitor ROM code size Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain $FF) Standard monitor mode entry if high voltage, VTST, is applied to IRQ
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* * * * * *
9.4 Functional Description
The monitor ROM receives and executes commands from a host computer. Figure 9-1 shows a example circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute host-computer code in RAM while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pull-up resistor.
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users.
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Monitor ROM (MON) Functional Description
VDD 10k (SEE NOTE 2)
VTST 10k C D + SW2 0.1 F
RST
HC908JG16 IRQ
VREG 0.1 F VDD VDD 0.1 F
4.7 F VDD 12MHz
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(SEE NOTE 3) 1 10 F + 3 4 10 F + 18 17 + 10 F VDD 20 pF 10 k DB-25 2 3 7 A 5 6 16 15 VDD 1 2 6 4 MC74HC125 14 3 10 k 5 VDD 10 k 7 VDD NOTES: 1. Affects high voltage entry to monitor mode only (SW2 at position C): SW1: Position A -- Bus clock = fXCLK / 2 SW1: Position B -- Bus clock = fXCLK 2. SW2: Position C -- High-voltage entry to monitor mode. SW2: Position D -- Low-voltage entry to monitor mode (with blank reset vector). See Section 20. for IRQ voltage level requirements. 3. SW3: Position E -- OSC1 directly driven by external oscillator. SW3: Position F -- OSC1 driven by crystal oscillator circuit. 10 k VDD (SEE NOTE 1) B SW1 20 + 12MHz 20 pF 10M 10 F F E E SW3 fXCLK
VSS
MC145407
OSC1
OSC2 F VDD
2
19
PTA3
PTA0
PTA1
PTE3 PTA2 10 k
Figure 9-1. Monitor Mode Circuit
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Monitor ROM (MON)
9.4.1 Entering Monitor Mode Table 9-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a POR and will allow communication at 19200 baud provided one of the following sets of conditions is met: 1. If IRQ = VTST: - External clock on OSC1 is 12MHz - PTA3 = high
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- PTE3 = high 2. If $FFFE & $FFFF is blank (contains $FF): - External clock on OSC1 is 12MHz - IRQ = VDD - PTE3 = high Table 9-1. Mode Entry Requirements and Options
PTA3(1) External Clock, fXCLK Bus Frequency, fBUS 12 MHz (fXCLK) $FFFE and $FFFF PTA2 PTA1 PTA0 PTE3 IRQ Comments High-voltage entry to monitor mode. 38400 baud communication on PTA0. COP disabled. High-voltage entry to monitor mode. 19200 baud communication on PTA0. COP disabled. Low-voltage entry to monitor mode. 19200 baud communication on PTA0. COP disabled. Enters user mode. If $FFFE and $FFFF is blank, MCU will encounter an illegal address reset.
VTST(2)
X
1
0 0 1 1 Factory use only
12 MHz
VTST(2)
X
1
1
0
1
1
12 MHz
6 MHz (fXCLK / 2)
VDD
BLANK (contain $FF)
1
X
X
X
1
12 MHz
6 MHz (fXCLK / 2)
VDD
NOT BLANK
1
X
X
X
X
12 MHz
6 MHz (fXCLK / 2)
Notes: 1. PTA3 = 0: Bypasses the divide-by-two prescaler to SIM when using VTST for monitor mode entry. 2. See Section 20. Electrical Specifications for VTST voltage level requirements.
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Monitor ROM (MON) Functional Description
If VTST is applied to IRQ and PTA3 is low upon monitor mode entry (Table 9-1 condition set 1), the bus frequency is a equal to the external clock, fXCLK. If PTA3 is high with VTST applied to IRQ upon monitor mode entry (Table 9-1 condition set 2), the bus frequency is a divide-by-two of the external clock. Holding the PTA3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if VTST is applied to IRQ. In this event, the OSCOUT frequency is equal to the OSCDCLK frequency.
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Entering monitor mode with VTST on IRQ, the COP is disabled as long as VTST is applied to either the IRQ or the RST. (See Section 8. System Integration Module (SIM) for more information on modes of operation.) If entering monitor mode without high voltage on IRQ and reset vector being blank ($FFFE and $FFFF) (Table 9-1 condition set 3, where IRQ applied voltage is VDD), then all port A pin requirements and conditions, including the PTA3 frequency divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit programming. Entering monitor mode with the reset vector being blank, the COP is always disabled regardless of the state of IRQ or the RST.
POR RESET
IS VECTOR BLANK? YES MONITOR MODE
NO
NORMAL USER MODE
EXECUTE MONITOR CODE
POR TRIGGERED? YES
NO
Figure 9-2. Low-Voltage Monitor Mode Entry Flowchart
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Monitor ROM (MON)
Figure 9-2. shows a simplified diagram of the monitor mode entry when the reset vector is blank and IRQ = VDD. An external clock of 12MHz is required for a baud rate of 19200. Enter monitor mode with the pin configuration shown in Figure 9-1 by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU waits for the host to send eight security bytes. (See 9.5 Security.) After the security bytes, the MCU sends a break signal (10 consecutive logic zeros) to the host, indicating that it is ready to receive a command. The break signal also provides a timing reference to allow the host to determine the necessary baud rate. In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. Table 9-2 is a summary of the vector differences between user mode and monitor mode. Table 9-2. Monitor Mode Vector Differences
Functions Modes COP User Monitor Enabled Disabled(1) Reset Vector High $FFFE $FEFE Reset Vector Low $FFFF $FEFF Break Vector High $FFFC $FEFC Break Vector Low $FFFD $FEFD SWI Vector High $FFFC $FEFC SWI Vector Low $FFFD $FEFD
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Notes: 1. If the high voltage (VTST) is removed from the IRQ pin or the RST pin, the SIM asserts its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the configuration register.
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Monitor ROM (MON) Functional Description
9.4.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical.
START BIT NEXT START BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP BIT
Figure 9-3. Monitor Data Format
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9.4.3 Break Signal A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
MISSING STOP BIT TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 9-4. Break Transaction 9.4.4 Baud Rate The communication baud rate is dependant on oscillator frequency, fXCLK. The state of PTA3 also affects baud rate if entry to monitor mode is by IRQ = VTST. When PTA3 is high, the divide by ratio is 625. If the PTA3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 312. Table 9-3. Monitor Baud Rate Selection
Monitor Mode Entry By: Oscillator Clock Frequency, fCLK 12 MHz IRQ = VTST Blank reset vector, IRQ = VDD 12 MHz 12 MHz PTA3 0 1 X Baud Rate 38400 bps 19200 bps 19200 bps
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Monitor ROM (MON)
9.4.5 Commands The monitor ROM uses the following commands: * * * * * READ (read memory) WRITE (write memory) IREAD (indexed read) IWRITE (indexed write) READSP (read stack pointer) RUN (run user program)
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*
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command.
NOTE:
Wait one bit time after each echo before sending the next byte.
FROM HOST
READ
READ
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
4 ECHO
1
4
1
4
1
3, 2
4 RETURN
Notes: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte.
Figure 9-5. Read Transaction
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Monitor ROM (MON) Functional Description
FROM HOST
WRITE 3 ECHO 1
WRITE 3
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
DATA
1
3
1
3
1
2, 3
Notes: 1 = Echo delay, 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte.
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Figure 9-6. Write Transaction A brief description of each monitor mode command is given in Table 9-4 through Table 9-9.
Table 9-4. READ (Read Memory) Command
Description Operand Data Returned Opcode Read byte from memory Specifies 2-byte address in high byte:low byte order Returns contents of specified address $4A Command Sequence
SENT TO MONITOR
READ
READ
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
ECHO
RETURN
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Monitor ROM (MON)
Table 9-5. WRITE (Write Memory) Command
Description Operand Data Returned Opcode Write byte to memory Specifics 2-byte address in high byte:low byte order; low byte followed by data byte None $49 Command Sequence
SEMT TO MONITOR
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WRITE
WRITE
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
DATA
ECHO
Table 9-6. IREAD (Indexed Read) Command
Description Operand Data Returned Opcode Read next 2 bytes in memory from last address accessed Specifies 2-byte address in high byte:low byte order Returns contents of next two addresses $1A Command Sequence
SENT TO MONITOR
IREAD
IREAD
DATA
DATA
ECHO
RETURN
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Monitor ROM (MON) Functional Description
Table 9-7. IWRITE (Indexed Write) Command
Description Operand Data Returned Opcode Write to last address accessed + 1 Specifies single data byte None $19 Command Sequence
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SENT TO MONITOR
IWRITE
IWRITE
DATA
DATA
ECHO
NOTE:
A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64k-byte memory map.
Table 9-8. READSP (Read Stack Pointer) Command
Description Operand Data Returned Opcode Reads stack pointer None Returns stack pointer in high byte:low byte order $0C Command Sequence
SENT TO MONITOR
READSP
READSP
SP HIGH
SP LOW
ECHO
RETURN
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Monitor ROM (MON)
Table 9-9. RUN (Run User Program) Command
Description Operand Data Returned Opcode Executes RTI instruction None None $28 Command Sequence
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SENT TO MONITOR
RUN
RUN
ECHO
The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6.
SP HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER ACCUMULATOR LOW BYTE OF INDEX REGISTER SP + 1 SP + 2 SP + 3 SP + 4
HIGH BYTE OF PROGRAM COUNTER SP + 5 LOW BYTE OF PROGRAM COUNTER SP + 6 SP + 7
Figure 9-7. Stack Pointer at Monitor Mode Entry
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Monitor ROM (MON) Security
9.5 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6-$FFFD. Locations $FFF6-$FFFD contain userdefined data.
NOTE:
Do not leave locations $FFF6-$FFFD blank. For security reasons, program locations $FFF6-$FFFD. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTA0. If the received bytes match those at locations $FFF6-$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on or an LVI reset occurs. If the reset was not a power-on or an LVI reset, security remains bypassed and security code entry is not required. (See Figure 9-8.)
VDD 4096 + 32 OSCDCLK CYCLES RST COMMAND 2 BYTE 8 ECHO 4 1 COMMAND ECHO BREAK 256 BUS CYCLES (MINIMUM) BYTE 1 BYTE 2 BYTE 8 1 BYTE 2 ECHO 1
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FROM HOST
PTA0 1 BYTE 1 ECHO FROM MCU 4
NOTES: 1 = Echo delay, 2 bit times. 2 = Data return delay, 2 bit times. 4 = Wait 1 bit time before sending next byte.
Figure 9-8. Monitor Mode Entry Timing
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Monitor ROM (MON)
Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6-$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command.
NOTE:
The MCU does not transmit a break character until after the host sends the eight security bytes. To determine whether the security code entered is correct, check to see if bit 6 of RAM address $80 is set. If it is, then the correct security code has been entered and FLASH can be accessed. If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank).
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9.5.1 Extended Security To further disable monitor mode functions, the monitor commands can be disabled by writing $7B to the FLASH location $FFD1 and $87 to the FLASH location $FFD0. Table 9-10 shows the security settings that affect monitor mode operations. Table 9-10. Monitor Mode Security
Extended Security Monitor Mode Entry Security BYPASSED NOT SET FAILED BYPASSED SET FAILED Monitor Commands Available Read/write of RAM and FLASH. Read/write of RAM. Read of FLASH disabled. FLASH can only be mass erased. Read/write of RAM and FLASH disabled. Read/write of RAM. Read of FLASH disabled. FLASH can only be mass erased.
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Technical Data -- MC68HC908JG16
Section 10. Timer Interface Module (TIM)
10.1 Contents
10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
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10.3 10.4
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 142 10.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 143 10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 143 10.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 144 10.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 145 10.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 10.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.9.1 TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . . 149 10.9.2 TIM Channel I/O Pins (PTE1/T1CH01:PTE2/T2CH01) . . . 149 10.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 150 10.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 153 10.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . .154 10.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
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Timer Interface Module (TIM) 10.2 Introduction
This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 10-1 is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
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NOTE:
TIM1 and TIM2 each have channel 0 and channel 1 I/Os connected together, forming a common I/O. Because of this common I/O, both channels should not be simultaneously configured for output compare functions, otherwise, port pin contention will occur.
10.3 Features
Features of the TIM include: * Two input capture/output compare channels on one common I/O: - Rising-edge, falling-edge, or any-edge input capture trigger - Set, clear, or toggle output compare action * * Buffered and unbuffered pulse-width-modulation (PWM) signal generation Programmable TIM clock input - 7-frequency internal bus clock prescaler selection - External TIM clock input (bus frequency /2 maximum) * * * Free-running or modulo up-count operation Toggle any channel pin on overflow TIM counter stop and reset bits
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Timer Interface Module (TIM) Pin Name Conventions
10.4 Pin Name Conventions
The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are T[1,2]CH01 (timer channel 01), where "1" is used to indicate TIM1 and "2" is used to indicate TIM2. The two TIMs share two I/O pins with two I/O port pins. The full names of the TIM I/O pins are listed in Table 10-1. The generic pin names appear in the text that follows. Table 10-1. Pin Name Conventions
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TIM Generic Pin Names: Full TIM Pin Names: TIM1 TIM2
T[1,2]CH01 PTE1/T1CH01
TCLK PTE0/TCLK
PTE2/T2CH01
NOTE:
References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TCH01 may refer generically to T1CH01 and T2CH01.
10.5 Functional Description
Figure 10-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. Channel 0 and channel 1 I/Os are connected together, forming a common I/O. Although the two TIM channels are programmable independently as input capture channels, the input capture signal will be the same for both channels. Output compare functions should only be enabled for one channel to avoid I/O contention.
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Timer Interface Module (TIM)
TCLK PRESCALER SELECT INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER 16-BIT COMPARATOR PRESCALER
PS2
PS1
PS0
TOF TOIE
INTERRUPT LOGIC
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TMODH:TMODL TOV0 CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A MS0B TOV1 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS0A CH1F CH01IE CH1IE INTERRUPT LOGIC ELS0B ELS0A CH1MAX PORT LOGIC CH0IE CH0F INTERRUPT LOGIC T[1,2]CH01 ELS0B ELS0A CH0MAX PORT LOGIC
Figure 10-1. TIM Block Diagram Figure 10-2 summarizes the timer registers.
NOTE:
References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC and T2SC.
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MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Timer Interface Module (TIM) Functional Description
Addr.
Register Name
Bit 7 TOF
6 TOIE
5 TSTOP
4 0 TRST
3 0
2 PS2
1 PS1 0 9
Bit 0 PS0 0 Bit 8
Read: Timer 1 Status and Control $000A Register Write: (T1SC) Reset: Read: Timer 1 Counter Register High Write: (T1CNTH) Reset: Read: Timer 1 Counter Register Low Write: (T1CNTL) Reset: Read: Timer 1 Counter Modulo Register High Write: (T1MODH) Reset: Read: Timer 1 Counter Modulo Register Low Write: (T1MODL) Reset:
0 0 Bit 15 0 14 1 13
0 12
0 11
0 10
$000C
0 Bit 7
0 6
0 5
0 4
0 3
0 2
0 1
0 Bit 0
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$000D
0 Bit 15 1 Bit 7 1 CH0F
0 14 1 6 1 CH0IE
0 13 1 5 1 MS0B 0 13
0 12 1 4 1 MS0A 0 12
0 11 1 3 1 ELS0B 0 11
0 10 1 2 1 ELS0A 0 10
0 9 1 1 1 TOV0 0 9
0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
$000E
$000F
Read: Timer 1 Channel 0 Status $0010 and Control Register Write: (T1SC0) Reset: Read: Timer 1 Channel 0 Register High Write: (T1CH0H) Reset: Read: Timer 1 Channel 0 Register Low Write: (T1CH0L) Reset:
0 0 Bit 15 0 14
$0011
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0012
Indeterminate after reset CH1F CH1IE 0 0 0 0 0 0 0 0 0 CH01IE MS1A ELS1B ELS1A TOV1 CH1MAX
Read: Timer 1 Channel 1 Status $0013 and Control Register Write: (T1SC1) Reset:
= Unimplemented
Figure 10-2. TIM I/O Register Summary (Sheet 1 of 3)
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Timer Interface Module (TIM)
Addr.
Register Name Read: Timer 1 Channel 1 Register High Write: (T1CH1H) Reset: Read: Timer 1 Channel 1 Register Low Write: (T1CH1L) Reset:
Bit 7 Bit 15
6 14
5 13
4 12
3 11
2 10
1 9
Bit 0 Bit 8
$0014
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0015
Indeterminate after reset TOF TOIE 0 0 Bit 15 0 14 1 13 TSTOP TRST 0 12 0 11 0 10 0 9 0 Bit 8 0 0 PS2 PS1 PS0
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Read: Timer 2 Status and Control $0040 Write: Register (T2SC) Reset: Read: Timer 2 Counter Register High Write: (T2CNTH) Reset: Read: Timer 2 Counter Register Low Write: (T2CNTL) Reset: Read: Timer 2 Counter Modulo Register High Write: (T2MODH) Reset: Read: Timer 2 Counter Modulo Register Low Write: (T2MODL) Reset:
$0042
0 Bit 7
0 6
0 5
0 4
0 3
0 2
0 1
0 Bit 0
$0043
0 Bit 15 1 Bit 7 1 CH0F
0 14 1 6 1 CH0IE
0 13 1 5 1 MS0B 0 13
0 12 1 4 1 MS0A 0 12
0 11 1 3 1 ELS0B 0 11
0 10 1 2 1 ELS0A 0 10
0 9 1 1 1 TOV0 0 9
0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
$0044
$0045
Read: Timer 2 Channel 0 Status $0046 and Control Register Write: (T2SC0) Reset: Read: Timer 2 Channel 0 Register High Write: (T2CH0H) Reset:
0 0 Bit 15 0 14
$0047
Indeterminate after reset = Unimplemented
Figure 10-2. TIM I/O Register Summary (Sheet 2 of 3)
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MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Timer Interface Module (TIM) Functional Description
Addr.
Register Name Read: Timer 2 Channel 0 Register Low Write: (T2CH0L) Reset:
Bit 7 Bit 7
6 6
5 5
4 4
3 3
2 2
1 1
Bit 0 Bit 0
$0048
Indeterminate after reset CH1F CH1IE 0 0 Bit 15 0 14 0 13 0 12 0 11 0 10 0 9 0 Bit 8 CH01IE MS1A ELS1B ELS1A TOV1 CH1MAX
Read: Timer 2 Channel 1 Status $0049 and Control Register Write: (T2SC1) Reset:
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$004A
Read: Timer 2 Channel 1 Register High Write: (T2CH1H) Reset: Read: Timer 2 Channel 1 Register Low Write: (T2CH1L) Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$004B
Indeterminate after reset = Unimplemented
Figure 10-2. TIM I/O Register Summary (Sheet 3 of 3) 10.5.1 TIM Counter Prescaler The TIM clock source can be one of the seven prescaler outputs or the TIM clock pin, PTE0/TCLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the TIM clock source.
10.5.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests.
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Timer Interface Module (TIM)
10.5.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. 10.5.3.1 Unbuffered Output Compare
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Any output compare channel can generate unbuffered output compare pulses as described in 10.5.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.
*
Technical Data 142 Timer Interface Module (TIM) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Timer Interface Module (TIM) Functional Description
10.5.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin.
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NOTE:
In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.
10.5.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 10-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0.
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Timer Interface Module (TIM)
The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000. See 10.10.1 TIM Status and Control Register.
OVERFLOW OVERFLOW OVERFLOW
PERIOD
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PULSE WIDTH TCHx
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 10-3. PWM Period and Pulse Width The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 10.5.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 10.5.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written.
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Timer Interface Module (TIM) Functional Description
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period.
*
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NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
10.5.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin.
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Technical Data 145
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Timer Interface Module (TIM)
NOTE:
In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals.
10.5.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure:
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1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 10-3.) b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 10-3.)
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Technical Data 146 Timer Interface Module (TIM) For More Information On This Product, Go to: www.freescale.com
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Timer Interface Module (TIM) Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. (See 10.10.4 TIM Channel Status and Control Registers.)
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10.6 Interrupts
The following TIM sources can generate interrupt requests: * TIM overflow flag (TOF) -- The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. TIM channel flags (CH1F:CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1. CHxF and CHxIE are in the TIM channel x status and control register.
*
10.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
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Timer Interface Module (TIM)
10.7.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction.
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10.7.2 Stop Mode The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
10.8 TIM During Break Interrupts
A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 8.8.3 SIM Break Flag Control Register (SBFCR).) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit.
Technical Data 148 Timer Interface Module (TIM) For More Information On This Product, Go to: www.freescale.com
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Timer Interface Module (TIM) I/O Signals
10.9 I/O Signals
Port E shares three of its pins with the TIM. PTE0/TCLK is an external clock input to the TIM prescaler. The two TIM channel I/O pins are PTE1/T1CH01 and PTE2/T2CH01.
10.9.1 TIM Clock Pin (PTE0/TCLK) PTE0/TCLK is an external clock input that can be the clock source for the TIM counter instead of the prescaled internal bus clock. Select the PTE0/TCLK input by writing logic 1s to the three prescaler select bits, PS[2:0]. (See 10.10.1 TIM Status and Control Register.) The minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is: 1 ------------------------------------ + t SU bus frequency The maximum TCLK frequency is: bus frequency / 2 PTE0/TCLK is available as a general-purpose I/O pin when not used as the TIM clock input. When the PTE0/TCLK pin is the TIM clock input, it is an input regardless of the state of the DDRE0 bit in data direction register E.
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10.9.2 TIM Channel I/O Pins (PTE1/T1CH01:PTE2/T2CH01) Each TIM I/O pin is programmable independently as an input capture pin or an output compare pin, or configured as buffered output compare or buffered PWM pins.
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Timer Interface Module (TIM) 10.10 I/O Registers
NOTE:
References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC and T2SC. These I/O registers control and monitor operation of the TIM: * * TIM status and control register (TSC) TIM counter registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0, TSC1) TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
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* * *
10.10.1 TIM Status and Control Register The TIM status and control register (TSC): * * * * * Enables TIM overflow interrupts Flags TIM overflows Stops the TIM counter Resets the TIM counter Prescales the TIM counter clock
Address: T1SC, $000A and T2SC, $0040 Bit 7 Read: Write: Reset: TOF TOIE 0 0 0 1 TSTOP TRST 0 0 0 0 0 6 5 4 0 3 0 PS2 PS1 PS0 2 1 Bit 0
= Unimplemented
Figure 10-4. TIM Status and Control Register (TSC)
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Timer Interface Module (TIM) I/O Registers
TOF -- TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE -- TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP -- TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active
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NOTE:
Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST -- TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000.
Technical Data Timer Interface Module (TIM) For More Information On This Product, Go to: www.freescale.com 151
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Timer Interface Module (TIM)
PS[2:0] -- Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 10-2 shows. Reset clears the PS[2:0] bits. Table 10-2. Prescaler Selection
PS2 0 0 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 TIM Clock Source Internal bus clock / 1 Internal bus clock / 2 Internal bus clock / 4 Internal bus clock / 8 Internal bus clock / 16 Internal bus clock / 32 Internal bus clock / 64 TCLK
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0 0 1 1 1 1
10.10.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break.
Address: T1CNTH, $000C and T2CNTH, $0042 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
= Unimplemented
Figure 10-5. TIM Counter Registers High (TCNTH)
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Timer Interface Module (TIM) I/O Registers
Address: T1CNTL, $000D and T2CNTL, $0043 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0
= Unimplemented
Figure 10-6. TIM Counter Registers Low (TCNTL)
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10.10.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: T1MODH, $000E and T2MODH, $0044 Bit 7 Read: Bit 15 Write: Reset: 1 1 1 1 1 1 1 1 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0
Figure 10-7. TIM Counter Modulo Register High (TMODH)
Address: T1MODL, $000F and T2MODL, $0045 Bit 7 Read: Bit 7 Write: Reset: 1 1 1 1 1 1 1 1 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0
Figure 10-8. TIM Counter Modulo Register Low (TMODL)
NOTE:
Reset the TIM counter before writing to the TIM counter modulo registers.
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Technical Data 153
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Timer Interface Module (TIM)
10.10.4 TIM Channel Status and Control Registers Each of the TIM channel status and control registers: * * * * * Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare, or PWM operation Selects high, low, or toggling output on output compare Selects rising edge, falling edge, or any edge as the active input capture trigger Selects output toggling on TIM overflow Selects 0% and 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation
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* * *
Address: T1SC0, $0010 and T2SC0, $0046 Bit 7 Read: Write: Reset: CH0F CH0IE 0 0 0 0 0 0 0 0 0 MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 6 5 4 3 2 1 Bit 0
Figure 10-9. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0013 and T2SC1, $0049 Bit 7 Read: Write: Reset: CH1F CH1IE 0 0 0 0 0 0 0 0 0 CH01IE MS1A ELS1B ELS1A TOV1 CH1MAX 6 5 4 3 2 1 Bit 0
Figure 10-10. TIM Channel 1 Status and Control Register (TSC1) CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers.
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Timer Interface Module (TIM) I/O Registers
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x
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CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled CH01IE -- CH0F and CH1F Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests when CH0F and CH1F are set. Reset clears the CH01IE bit. 1 = CPU interrupt requests when CH0F and CH1F are set 0 = No CPU interrupt requests when CH0F and CH1F are set MS0B -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MS0B exists only in the TIM1 channel 0 and TIM2 channel 0 status and control registers. Setting MS0B disables the channel 1 status and control register. Reset clears the MS0B bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA -- Mode Select Bit A When ELSxB:ELSxA 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 10-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Timer Interface Module (TIM) For More Information On This Product, Go to: www.freescale.com Technical Data 155
Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See Table 10-3. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register. ELSxB and ELSxA -- Edge/Level Select Bits
Freescale Semiconductor, Inc...
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 10-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Table 10-3. Mode, Edge, and Level Selection
MS0B:MSxA X0 X1 00 00 00 01 01 01 1X 1X 1X ELSxB:ELSxA 00 Output preset 00 01 10 11 01 10 11 01 10 11 Output compare or PWM(1) Buffered output compare or buffered PWM Input capture Mode Configuration Pin under port control; initial output level high Pin under port control; initial output level low Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare
Notes: 1. Enable only one channel for unbuffered output compare or PWM functions. Avoid the following configuration: MS0B = 0, MS0A = 1, MS1A = 1, and ELSxB:A 00
Technical Data 156 Timer Interface Module (TIM) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Timer Interface Module (TIM) I/O Registers
NOTE:
Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. TOVx -- Toggle On Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow 0 = Channel x pin does not toggle on TIM counter overflow
Freescale Semiconductor, Inc...
NOTE:
When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 10-11 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW PERIOD TCHx OVERFLOW OVERFLOW OVERFLOW OVERFLOW
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 10-11. CHxMAX Latency 10.10.5 TIM Channel Registers These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown.
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Timer Interface Module (TIM) For More Information On This Product, Go to: www.freescale.com Technical Data 157
Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: T1CH0H, $0011 and T2CH0H, $0047 Bit 7 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Freescale Semiconductor, Inc...
Read: Bit 15 Write: Reset: Indeterminate after reset
Figure 10-12. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0012 and T2CH0L $0048 Bit 7 Read: Bit 7 Write: Reset: Indeterminate after reset 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0
Figure 10-13. TIM Channel 0 Register Low (TCH0L)
Address: T1CH1H, $0014 and T2CH1H, $004A Bit 7 Read: Bit 15 Write: Reset: Indeterminate after reset 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0
Figure 10-14. TIM Channel 1 Register High (TCH1H)
Address: T1CH1L, $0015 and T2CH1L, $004B Bit 7 Read: Bit 7 Write: Reset: Indeterminate after reset 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0
Figure 10-15. TIM Channel 1 Register Low (TCH1L)
Technical Data 158 Timer Interface Module (TIM) For More Information On This Product, Go to: www.freescale.com MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Technical Data -- MC68HC908JG16
Section 11. Universal Serial Bus Module (USB)
11.1 Contents
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Freescale Semiconductor, Inc...
11.3 11.4
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11.5.1 USB Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.5.1.1 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 11.5.1.2 Packet Identifier Field . . . . . . . . . . . . . . . . . . . . . . . . . .169 11.5.1.3 Address Field (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . .170 11.5.1.4 Endpoint Field (ENDP). . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.5.1.5 Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . 170 11.5.1.6 End-of-Packet (EOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.5.2 Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 11.5.3 Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.5.4 Resume After Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.5.4.1 Host Initiated Resume . . . . . . . . . . . . . . . . . . . . . . . . . .173 11.5.4.2 USB Reset Signalling. . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.5.4.3 Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.5.5 Low-Speed Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.6 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
11.7 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7.1 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7.2 USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7.2.1 Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . 176 11.7.2.2 Low Speed (1.5 Mbps) Driver Characteristics . . . . . . . . 176 11.7.2.3 Receiver Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.2.4 Data Source Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.2.5 Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . .178
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com Technical Data 159
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB)
11.7.3 USB Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Freescale Semiconductor, Inc...
11.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.8.1 USB Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.8.2 USB Interrupt Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . .181 11.8.3 USB Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .183 11.8.4 USB Interrupt Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .186 11.8.5 USB Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.8.6 USB Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.8.7 USB Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.8.8 USB Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.8.9 USB Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.8.10 USB Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.8.11 USB Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.8.12 USB Endpoint 0 Data Registers . . . . . . . . . . . . . . . . . . . . . 196 11.8.13 USB Endpoint 1 Data Registers . . . . . . . . . . . . . . . . . . . . . 197 11.8.14 USB Endpoint 2 Data Registers . . . . . . . . . . . . . . . . . . . . . 198 11.9 USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.9.1 USB End-of-Transaction Interrupt . . . . . . . . . . . . . . . . . . .199 11.9.1.1 Receive Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . .200 11.9.1.2 Transmit Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . 202 11.9.1.3 Transmit Endpoint 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 11.9.1.4 Transmit Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.9.1.5 Receive Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.9.2 Resume Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.9.3 End-of-Packet Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
11.2 Introduction
This section describes the universal serial bus (USB) module. The USB module is designed to serve as a low-speed (LS) USB device per the Universal Serial Bus Specification Rev. 2.0. Control and interrupt data transfers are supported. Endpoint 0 functions as a transmit/receive control endpoint; endpoint 1 functions as interrupt transmit endpoint; endpoint 2 functions as interrupt transmit or receive endpoint.
Technical Data 160 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) Features
11.3 Features
Features of the USB module include: * * * * Universal Serial Bus Specification 2.0 low-speed functions 1.5 Mbps data rate On-chip 3.3V regulator Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer Endpoint 1 with 8-byte transmit buffer Endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer USB data control logic: - Control endpoint 0 and interrupt endpoints 1 and 2 - Packet decoding/generation - CRC generation and checking - NRZI (Non-Return-to Zero Inserted) encoding/decoding - Bit-stuffing * USB reset options: - Internal MCU reset generation - CPU interrupt request generation * * Suspend and resume operations, with remote wakeup support USB-generated interrupts: - Transaction interrupt driven - Resume interrupt - End-of-packet interrupt - USB reset * STALL, NAK, and ACK handshake generation
Freescale Semiconductor, Inc...
* * *
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
Technical Data 161
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) 11.4 Pin Name Conventions
The USB share two I/O pins with two port E I/O pins. The full name of the USB I/O pin is listed in Table 11-1. The generic pin name appear in the text that follows. Table 11-1. USB Module Pin Name Conventions
USB Generic Pin Names: Full USB Pin Names: D+ PTE3/D+ D- PTE4/D-
Freescale Semiconductor, Inc...
Addr.
Register Name
Bit 7
6 0 RSTFR 0 STALL2 0 0 TX1STR
5 0 TXD2FR 0 TX2E 0
4 0 RXD2FR 0 RX2E 0
3 0
2 0
1 0
Bit 0 0 RXD0FR 0 TP2SIZ0 0
$0018
Read: 0 USB Interrupt Register 2 Write: EOPFR (UIR2) Reset: 0 Read: USB Control Register 2 Write: (UCR2) Reset: Read: USB Control Register 3 Write: (UCR3) Reset: T2SEQ 0 TX1ST
TXD1FR RESUMFR TXD0FR 0 TP2SIZ3 0 0 0 TP2SIZ2 0 0 TP2SIZ1 0
$0019
$001A
OSTALL0 ISTALL0 0 0
PULLEN ENABLE2 ENABLE1 0* 0 0
0
0
0
* PULLEN bit is reset by POR or LVI reset only. Read: USB Control Register 4 Write: (UCR4) Reset: 0 0 0 0 0 FUSBO 0 UE0R02 UE0T02 FDP 0 UE0R01 UE0T01 FDM 0 UE0R00 UE0T00
$001B
0
0 UE0R06 UE0T06
0 UE0R05 UE0T05
0 UE0R04 UE0T04
0 UE0R03 UE0T03
$0020
Read: UE0R07 USB Endpoint 0 Data Register 0 Write: UE0T07 (UE0D0) Reset: Read: UE0R17 USB Endpoint 0 Data Register 1 Write: UE0T17 (UE0D1) Reset:
Unaffected by reset UE0R16 UE0T16 UE0R15 UE0T15 UE0R14 UE0T14 UE0R13 UE0T13 UE0R12 UE0T12 UE0R11 UE0T11 UE0R10 UE0T10
$0021
Unaffected by reset = Unimplemented U = Unaffected by reset
Figure 11-1. USB I/O Register Summary (Sheet 1 of 4)
Technical Data 162 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) Pin Name Conventions
Addr.
Register Name
Bit 7
6 UE0R26 UE0T26
5 UE0R25 UE0T25
4 UE0R24 UE0T24
3 UE0R23 UE0T23
2 UE0R22 UE0T22
1 UE0R21 UE0T21
Bit 0 UE0R20 UE0T20
$0022
Read: UE0R27 USB Endpoint 0 Data Register 2 Write: UE0T27 (UE0D2) Reset: Read: UE0R37 USB Endpoint 0 Data Register 3 Write: UE0T37 (UE0D3) Reset: Read: UE0R47 USB Endpoint 0 Data Register 4 Write: UE0T47 (UE0D4) Reset: Read: UE0R57 USB Endpoint 0 Data Register 5 Write: UE0T57 (UE0D5) Reset: Read: UE0R67 USB Endpoint 0 Data Register 6 Write: UE0T67 (UE0D6) Reset: Read: UE0R77 USB Endpoint 0 Data Register 7 Write: UE0T77 (UE0D7) Reset: Read: USB Endpoint 1 Data Register 0 Write: UE1T07 (UE1D0) Reset: Read: USB Endpoint 1 Data Register 1 Write: UE1T17 (UE1D1) Reset: Read: USB Endpoint 1 Data Register 2 Write: UE1T27 (UE1D2) Reset: Read: USB Endpoint 1 Data Register 3 Write: UE1T37 (UE1D3) Reset:
Unaffected by reset UE0R36 UE0T36 UE0R35 UE0T35 UE0R34 UE0T34 UE0R33 UE0T33 UE0R32 UE0T32 UE0R31 UE0T31 UE0R30 UE0T30
$0023
Unaffected by reset UE0R46 UE0T46 UE0R45 UE0T45 UE0R44 UE0T44 UE0R43 UE0T43 UE0R42 UE0T42 UE0R41 UE0T41 UE0R40 UE0T40
Freescale Semiconductor, Inc...
$0024
Unaffected by reset UE0R56 UE0T56 UE0R55 UE0T55 UE0R54 UE0T54 UE0R53 UE0T53 UE0R52 UE0T52 UE0R51 UE0T51 UE0R50 UE0T50
$0025
Unaffected by reset UE0R66 UE0T66 UE0R65 UE0T65 UE0R64 UE0T64 UE0R63 UE0T63 UE0R62 UE0T62 UE0R61 UE0T61 UE0R60 UE0T60
$0026
Unaffected by reset UE0R76 UE0T76 UE0R75 UE0T75 UE0R74 UE0T74 UE0R73 UE0T73 UE0R72 UE0T72 UE0R71 UE0T71 UE0R70 UE0T70
$0027
Unaffected by reset
$0028
UE1T06
UE1T05
UE1T04
UE1T03
UE1T02
UE1T01
UE1T00
Unaffected by reset
$0029
UE1T16
UE1T15
UE1T14
UE1T13
UE1T12
UE1T11
UE1T10
Unaffected by reset
$002A
UE1T26
UE1T25
UE1T24
UE1T23
UE1T22
UE1T21
UE1T20
Unaffected by reset
$002B
UE1T36
UE1T35
UE1T34
UE1T33
UE1T32
UE1T31
UE1T30
Unaffected by reset = Unimplemented U = Unaffected by reset
Figure 11-1. USB I/O Register Summary (Sheet 2 of 4)
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
Technical Data 163
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB)
Addr. $002C
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: USB Endpoint 1 Data Register 4 Write: UE1T47 (UE1D4) Reset: Read: USB Endpoint 1 Data Register5 Write: UE1T57 (UE1D5) Reset: Read: USB Endpoint 1 Data Register 6 Write: UE1T67 (UE1D6) Reset: Read: USB Endpoint 1 Data Register 7 Write: UE1T77 (UE1D7) Reset: Read: UE2R07 USB Endpoint 2 Data Register 0 Write: UE2T07 (UE2D0) Reset: Read: UE2R17 USB Endpoint 2 Data Register 1 Write: UE2T17 (UE2D1) Reset: Read: UE2R27 USB Endpoint 2 Data Register 2 Write: UE2T27 (UE2D2) Reset: Read: UE2R37 USB Endpoint 2 Data Register 3 Write: UE2T37 (UE2D3) Reset: Read: UE2R47 USB Endpoint 2 Data Register 4 Write: UE2T47 (UE2D4) Reset: Read: UE2R57 USB Endpoint 2 Data Register 5 Write: UE2T57 (UE2D5) Reset:
UE1T46
UE1T45
UE1T44
UE1T43
UE1T42
UE1T41
UE1T40
Unaffected by reset
$002D
UE1T56
UE1T55
UE1T54
UE1T53
UE1T52
UE1T51
UE1T50
Unaffected by reset
$002E
Freescale Semiconductor, Inc...
UE1T66
UE1T65
UE1T64
UE1T63
UE1T62
UE1T61
UE1T60
Unaffected by reset
$002F
UE1T76
UE1T75
UE1T74
UE1T73
UE1T72
UE1T71
UE1T70
Unaffected by reset UE2R06 UE2T06 UE2R05 UE2T05 UE2R04 UE2T04 UE2R03 UE2T03 UE2R02 UE2T02 UE2R01 UE2T01 UE2R00 UE2T00
$0030
Unaffected by reset UE2R16 UE2T16 UE2R15 UE2T15 UE2R14 UE2T14 UE2R13 UE2T13 UE2R12 UE2T12 UE2R11 UE2T11 UE2R10 UE2T10
$0031
Unaffected by reset UE2R26 UE2T26 UE2R25 UE2T25 UE2R24 UE2T24 UE2R23 UE2T23 UE2R22 UE2T22 UE2R21 UE2T21 UE2R20 UE2T20
$0032
Unaffected by reset UE2R36 UE2T36 UE2R35 UE2T35 UE2R34 UE2T34 UE2R33 UE2T33 UE2R32 UE2T32 UE2R31 UE2T31 UE2R30 UE2T30
$0033
Unaffected by reset UE2R46 UE2T46 UE2R45 UE2T45 UE2R44 UE2T44 UE2R43 UE2T43 UE2R42 UE2T42 UE2R41 UE2T41 UE2R40 UE2T40
$0034
Unaffected by reset UE2R56 UE2T56 UE2R55 UE2T55 UE2R54 UE2T54 UE2R53 UE2T53 UE2R52 UE2T52 UE2R51 UE2T51 UE2R50 UE2T50
$0035
Unaffected by reset = Unimplemented U = Unaffected by reset
Figure 11-1. USB I/O Register Summary (Sheet 3 of 4)
Technical Data 164 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) Pin Name Conventions
Addr.
Register Name
Bit 7
6 UE2R66 UE2T66
5 UE2R65 UE2T65
4 UE2R64 UE2T64
3 UE2R63 UE2T63
2 UE2R62 UE2T62
1 UE2R61 UE2T61
Bit 0 UE2R60 UE2T60
$0036
Read: UE2R67 USB Endpoint 2 Data Register 6 Write: UE2T67 (UE2D6) Reset: Read: UE2R77 USB Endpoint 2 Data Register 7 Write: UE2T77 (UE2D7) Reset: Read: USBEN USB Address Register Write: (UADDR) Reset: 0*
Unaffected by reset UE2R76 UE2T76 UE2R75 UE2T75 UE2R74 UE2T74 UE2R73 UE2T73 UE2R72 UE2T72 UE2R71 UE2T71 UE2R70 UE2T70
$0037
Unaffected by reset UADD6 0 UADD5 0 UADD4 0 UADD3 0 UADD2 0 UADD1 0 UADD0 0
Freescale Semiconductor, Inc...
$0038
* USBEN bit is reset by POR or LVI reset only. Read: USB Interrupt Register 0 Write: (UIR0) Reset: Read: USB Interrupt Register 1 Write: (UIR1) Reset: Read: USB Control Register 0 Write: (UCR0) Reset: Read: USB Control Register 1 Write: (UCR1) Reset: EOPIE 0 EOPF SUSPND 0 RSTF TXD2IE 0 TXD2F RXD2IE 0 RXD2F TXD1IE 0 TXD1F 0 TXD0IE 0 TXD0F RXD0IE 0 RXD0F
$0039
0 RESUMF
$003A
0 T0SEQ 0 T1SEQ 0
0 0
0 TX0E 0 TX1E 0 0
0 RX0E 0
0 TP0SIZ3 0
0 TP0SIZ2 0 TP1SIZ2 0 RP0SIZ2
0 TP0SIZ1 0 TP1SIZ1 0 RP0SIZ1
0 TP0SIZ0 0 TP1SIZ0 0 RP0SIZ0
$003B
0 STALL1 0 SETUP
$003C
FRESUM TP1SIZ3 0 0 0 RP0SIZ3
$003D
Read: R0SEQ USB Status Register 0 Write: (USR0) Reset: Read: R2SEQ USB Status Register 1 Write: (USR1) Reset: U
Unaffected by reset TXACK TXNAK TXSTL RP2SIZ3 RP2SIZ2 RP2SIZ1 RP2SIZ0
$003E
0
0
0
U
U
U
U
= Unimplemented
U = Unaffected by reset
Figure 11-1. USB I/O Register Summary (Sheet 4 of 4)
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
Technical Data 165
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) 11.5 Functional Description
Figure 11-2 shows the block diagram of the USB module. The USB module manages communications between the host and the USB function. The module is partitioned into three functional blocks. These blocks consist of a dual-function transceiver, the USB control logic, and the endpoint registers. The blocks are further detailed later in this section (see 11.7 Hardware Description).
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RCV USB CONTROL LOGIC VPOUT VMOUT VPIN VMIN TRANSCEIVER D+ USB UPSTREAM PORT
D-
FROM OSC
6MHZ
CPU BUS
USB REGISTERS
Figure 11-2. USB Block Diagram
Technical Data 166 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) Functional Description
11.5.1 USB Protocol Figure 11-3 shows the various transaction types supported by the USB module. The transactions are portrayed as error free. The effect of errors in the data flow are discussed later.
ENDPOINT 0 TRANSACTIONS: Control Write SETUP DATA0 ACK OUT DATA1 ACK
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OUT
DATA0
ACK
OUT
DATA0/1
ACK
IN Control Read SETUP DATA0 ACK IN DATA1
DATA1
ACK
ACK
IN
DATA0
ACK
IN
DATA0/1
ACK
OUT No-Data Control SETUP DATA0 ACK IN DATA1
DATA1
ACK
ACK
ENDPOINTS 1 & 2 TRANSACTIONS: KEY: Interrupt IN DATA0/1 ACK Unrelated Bus Traffic Host Generated Device Generated
Bulk Transmit IN DATA0/1 ACK
Figure 11-3. Supported Transaction Types Per Endpoint
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
Technical Data 167
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB)
Each USB transaction is comprised of a series of packets. The USB module supports the packet types shown in Figure 11-4. Token packets are generated by the USB host and decoded by the USB device. Data and handshake packets are both decoded and generated by the USB device, depending on the type of transaction.
Token Packet: IN OUT SYNC PID PID ADDR ENDP CRC5 EOP
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SETUP Data Packet: DATA0 DATA1 Handshake Packet: ACK NAK STALL SYNC PID PID EOP SYNC PID PID DATA 0 - 8 Bytes CRC16 EOP
Figure 11-4. Supported USB Packet Types The following sections detail each segment used to form a complete USB transaction. 11.5.1.1 Sync Pattern The NRZI bit pattern shown in Figure 11-5 is used as a synchronization pattern and is prefixed to each packet. This pattern is equivalent to a data pattern of seven 0s followed by a 1 ($80).
SYNC PATTERN NRZI Data Encoding Idle PID0 PID1
Figure 11-5. Sync Pattern
Technical Data 168 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) Functional Description
The start of a packet (SOP) is signaled by the originating port by driving the D+ and D- lines from the idle state (also referred to as the J state) to the opposite logic level (also referred to as the K state). This switch in levels represents the first bit of the sync field. Figure 11-6 shows the data signaling and voltage levels for the start of packet and the sync pattern.
VOH (min.)
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VSE (max) VSE (min.) VOL (min.) VSS FIRST BIT OF PACKET BUS IDLE SOP END OF SYNC
Figure 11-6. SOP, Sync Signaling, and Voltage Levels 11.5.1.2 Packet Identifier Field The packet identifier field is an 8-bit number comprised of the 4-bit packet identification and its complement. The field follows the sync pattern and determines the direction and type of transaction on the bus. Table 11-2 shows the packet identifier values for the supported packet types. Table 11-2. Supported Packet Identifiers
Packet Identifier Value %1001 %0001 %1101 %0011 %1011 %0010 %1010 %1110 MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com Packet Identifier Type IN Token OUT Token SETUP Token DATA0 Packet DATA1 Packet ACK Handshake NAK Handshake STALL Handshake Technical Data 169
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Universal Serial Bus Module (USB)
11.5.1.3 Address Field (ADDR) The address field is a 7-bit number that is used to select a particular USB device. This field is compared to the lower seven bits of the UADDR register to determine if a given transaction is targeting the MCU USB device. 11.5.1.4 Endpoint Field (ENDP) The endpoint field is a 4-bit number that is used to select a particular endpoint within a USB device. For the MCU, this will be a binary number between 0 and 2 inclusive. Any other value will cause the transaction to be ignored. 11.5.1.5 Cyclic Redundancy Check (CRC) Cyclic redundancy checks are used to verify the address and data stream of a USB transaction. This field is five bits wide for token packets and 16 bits wide for data packets. CRCs are generated in the transmitter and sent on the USB data lines after both the endpoint field and the data field. 11.5.1.6 End-of-Packet (EOP) The single-ended 0 (SE0) state is used to signal an end-of-packet (EOP). The single-ended 0 state is indicated by both D+ and D- being below 0.8V. EOP will be signaled by driving D+ and D- to the singleended 0 state for two bit times followed by driving the lines to the idle state for one bit time. The transition from the single-ended 0 to the idle state defines the end of the packet. The idle state is asserted for one bit time and then both the D+ and D- output drivers are placed in their highimpedance state. The bus termination resistors hold the bus in the idle state. Figure 11-7 shows the data signaling and voltage levels for an end-of-packet transaction.
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Technical Data 170 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) Functional Description
LAST BIT OF PACKET EOP STROBE VOH (min.)
BUS DRIVEN TO IDLE STATE BUS FLOATS BUS IDLE
VSE (max) VSE (min.) VOL (min.) VSS
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Figure 11-7. EOP Transaction Voltage Levels The width of the SE0 in the EOP is about two bit times. The EOP width is measured with the same capacitive load used for maximum rise and fall times and is measured at the same level as the differential signal crossover points of the data lines.
tPeriod DATA CROSSOVER LEVEL
DIFFERENTIAL DATA LINES
EOP WIDTH
Figure 11-8. EOP Width Timing
11.5.2 Reset Signaling The USB module will detect a reset signaled on the bus by the presence of an extended SE0 at the USB data pins of a device. The MCU seeing a single-ended 0 on its USB data inputs for more than 8s treats that signal as a reset. A USB sourced reset will hold the MCU in reset for the duration of the reset on the USB bus. The USB bit in the reset status register (SRSR) will be set after the internal reset is removed. Refer to 8.8.2 SIM Reset Status Register (SRSR) for more detail. The MCU's reset recovery sequence is detailed in Section 8. System Integration Module (SIM).
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Universal Serial Bus Module (USB)
The reset flag bit (RSTF) in the USB interrupt register 1 (UIR1) also will be set after the internal reset is removed. Refer to 11.8.3 USB Interrupt Register 1 for more detail. After a reset is removed, the device will be in the default, but not yet addressed or configured state (refer to Section 9.1 USB Device States of the Universal Serial Bus Specification Rev. 2.0). The device must be able to accept a device address via a SET_ADDRESS command (refer to Section 9.4 Standard Device Request in the Universal Serial Bus Specification Rev. 2.0) no later than 10ms after the reset is removed.
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Reset can wake a device from the suspended mode.
NOTE:
USB reset can be configured not to generate a reset signal to the CPU by setting the URSTD bit of the configuration register (see Section 5. Configuration Register (CONFIG)). When a USB reset is detected, the CPU generates an USB interrupt.
11.5.3 Suspend The MCU supports suspend mode for low power. Suspend mode should be entered when the USB data lines are in the idle state for more than 3ms. Entry into suspend mode is controlled by the SUSPND bit in the USB interrupt register. Any low-speed bus activity should keep the device out of the suspend state. Low-speed devices are kept awake by periodic low-speed EOP signals from the host. This is referred to as low speed keep alive (refer to Section 11.8.4.1 Low-speed Keep-alive in the Universal Serial Bus Specification Rev. 2.0). Firmware should monitor the EOPF flag and enter suspend mode by setting the SUSPND bit if an EOP is not detected for 3ms. Per the USB specification, the bus powered USB system is required to draw less than 500A from the VDD supply when in the suspend state. This includes the current supplied by the voltage regulator to the 1.5k to ground termination resistors placed at the host end of the USB bus. This low-current requirement means that firmware is responsible for entering stop mode once the USB module has been placed in the suspend state.
Technical Data 172 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) Functional Description
11.5.4 Resume After Suspend The MCU can be activated from the suspend state by normal bus activity, a USB reset signal, or by a forced resume driven from the MCU. 11.5.4.1 Host Initiated Resume The host signals resume by initiating resume signalling (K state) for at least 20ms followed by a standard low-speed EOP signal. This 20ms ensures that all devices in the USB network are awakened.
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After resuming the bus, the host must begin sending bus traffic within 3ms to prevent the device from re-entering suspend mode. 11.5.4.2 USB Reset Signalling Reset can wake a device from the suspended mode. 11.5.4.3 Remote Wakeup The MCU also supports the remote wakeup feature. The firmware has the ability to exit suspend mode by signaling a resume state to the upstream host or hub. A non-idle state (K state) on the USB data lines is accomplished by asserting the FRESUM bit in the UCR1 register. When using the remote wakeup capability, the firmware must wait for at least 5ms after the bus is in the idle state before sending the remote wakeup resume signaling. This allows the upstream devices to get into their suspend state and prepare for propagating resume signaling. The FRESUM bit should be asserted to cause the resume state on the USB data lines for at least 10ms, but not more than 15ms. Note that the resume signalling is controlled by the FRESUM bit and meeting the timing specifications is dependent on the firmware. When FRESUM is cleared by firmware, the data lines will return to their high-impedance state. Refer to register definitions (see 11.8.6 USB Control Register 1) for more information about how the force resume (FRESUM) bit can be used to initiate the remote wakeup feature.
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Technical Data 173
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Universal Serial Bus Module (USB)
11.5.5 Low-Speed Device Low-speed devices are configured by the position of a pull-up resistor on the USB D- pin of the MCU. Low-speed devices are terminated as shown in Figure 11-9 with the pull-up on the D- line.
VREG (3.3V)
MCU
1.5 k D+ USB LOW-SPEED CABLE D-
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Figure 11-9. External Low-Speed Device Configuration For low-speed transmissions, the transmitter's EOP width must be between 1.25s and 1.50s. These ranges include timing variations due to differential buffer delay and rise/fall time mismatches and to noise and other random effects. A low-speed receiver must accept a 670ns SE0 followed by a J transition as a valid EOP. An SE0 shorter than 330ns or an SE0 not followed by a J transition are rejected as an EOP. Any SE0 that is 8s or longer is automatically a reset.
11.6 Clock Requirements
The low-speed data rate is nominally 1.5 Mbps. The OSCXCLK/2 (6MHz) signal driven by the oscillator circuits is the clock source for the USB module and requires that a 12MHz oscillator circuit be connected to the OSC1 and OSC2 pins. The permitted frequency tolerance for lowspeed functions is approximately 1.5% (15,000 ppm). This tolerance includes inaccuracies from all sources: initial frequency accuracy, crystal capacitive loading, supply voltage on the oscillator, temperature, and aging. The jitter in the low-speed data rate must be less than 10ns.
Technical Data 174 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) Hardware Description
11.7 Hardware Description
The USB module as previously shown in Figure 11-2 contains three functional blocks: the low-speed USB transceiver, the USB control logic, and the USB registers. The following details the function of the regulator, transceiver, and control logic. See 11.8 I/O Registers for details of register settings.
11.7.1 Voltage Regulator
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The USB data lines are required by the USB specification to have an output voltage between 2.8V and 3.6V. The data lines also are required to have an external 1.5k pull-up resistor connected between a data line and a voltage source between 3.0V and 3.6V. Figure 11-10 shows the worst case electrical connection for the voltage regulator.
4.0V TO 5.5V
3.3V REGULATOR R1 LOW-SPEED TRANSCEIVER D+
USB DATA LINES
USB CABLE D- R1 = 1.5k 5% R2 = 15k 5% R2 R2
HOST OR HUB
Figure 11-10. Regulator Electrical Connections
11.7.2 USB Transceiver The USB transceiver provides the physical interface to the USB D+ and D- data lines. The transceiver is composed of two parts: an output drive circuit and a receiver.
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Universal Serial Bus Module (USB)
11.7.2.1 Output Driver Characteristics The USB transceiver uses a differential output driver to drive the USB data signal onto the USB cable. The static output swing of the driver in its low state is below the VOL of 0.3V with a 1.5k load to 3.6V and in its high state is above the VOH of 2.8V with a 15k load to ground. The output swings between the differential high and low state are well balanced to minimize signal skew. Slew rate control on the driver is used to minimize the radiated noise and cross talk. The driver's outputs support 3-state operation to achieve bidirectional half duplex operation. The driver can tolerate a voltage on the signal pins of -1.0V to 5.5V with respect to local ground reference without damage. 11.7.2.2 Low Speed (1.5 Mbps) Driver Characteristics The rise and fall time of the signals on this cable are greater than 75ns and less than 300ns. The edges are matched to within 20% to minimize RFI emissions and signal skew. USB data transmission is done with differential signals. A differential input receiver is used to accept the USB data signal. A differential 1 on the bus is represented by D+ being at least 200mV more positive than D- as seen at the receiver, and a differential 0 is represented by D- being at least 200mV more positive than D+ as seen at the receiver. The signal cross over point must be between 1.3V and 2.0V.
ONE BIT TIME (1.5 Mb/s)
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VSE (max) VSE (min.) VSS
SIGNAL PINS PASS OUTPUT SPEC LEVELS WITH MINIMAL REFLECTIONS AND RINGING
Figure 11-11. Receiver Characteristics
Technical Data 176 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Universal Serial Bus Module (USB) Hardware Description
The receiver features an input sensitivity of 200mV when both differential data inputs are in the differential common mode range of 0.8V to 2.5V as shown in Figure 11-12. In addition to the differential receiver, there is a single-ended receiver (schmitt trigger) for each of the two data lines.
Differential Input voltage Range Differential Output Crossover Voltage Range
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-1.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
5.5
INPUT VOLTAGE RANGE (VOLTS)
Figure 11-12. Differential Input Sensitivity Range 11.7.2.3 Receiver Data Jitter The data receivers for all types of devices must be able to properly decode the differential data in the presence of jitter. The more of the bit time that any data edge can occupy and still be decoded, the more reliable the data transfer will be. Data receivers are required to decode differential data transitions that occur in a window plus and minus a nominal quarter bit time from the nominal (centered) data edge position. Jitter will be caused by the delay mismatches and by mismatches in the source and destination data rates (frequencies). The receive data jitter budget for low speed is given in Section 20. Electrical Specifications. The specification includes the consecutive (next) and paired transition values for each source of jitter. 11.7.2.4 Data Source Jitter The source of data can have some variation (jitter) in the timing of edges of the data transmitted. The time between any set of data transitions is N x TPeriod jitter time, where N is the number of bits between the transitions and TPeriod is defined as the actual period of the data rate. The data jitter is measured with the same capacitive load used for maximum rise and fall times and is measured at the crossover points of the data lines as shown in Figure 11-13.
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Universal Serial Bus Module (USB)
tPeriod DIFFERENTIAL DATA LINES CROSSOVER POINTS
JITTER
CONSECUTIVE TRANSITIONS
PAIRED TRANSITIONS
Figure 11-13. Data Jitter
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For low-speed transmissions, the jitter time for any consecutive differential data transitions must be within 25ns and within 10ns for any set of paired differential data transitions. These jitter numbers include timing variations due to differential buffer delay, rise/fall time mismatches, internal clock source jitter, noise and other random effects. 11.7.2.5 Data Signal Rise and Fall Time The output rise time and fall time are measured between 10% and 90% of the signal. Edge transition time for the rising and falling edges of lowspeed signals is 75ns (minimum) into a capacitive load (CL) of 200pF and 300ns (maximum) into a capacitive load of 600pF. The rising and falling edges should be transitioning (monotonic) smoothly when driving the cable to avoid excessive EMI.
RISE TIME
+
FALL TIME 90% 90%
CL
DIFFERENTIAL DATA LINES 10% 10% tR tF
+
CL
LOW SPEED: 75ns at CL = 200pF, 300ns at CL = 600 pF
Figure 11-14. Data Signal Rise and Fall Time
Technical Data 178 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
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Universal Serial Bus Module (USB) I/O Registers
11.7.3 USB Control Logic The USB control logic manages data movement between the CPU and the transceiver. The control logic handles both transmit and receive operations on the USB. It contains the logic used to manipulate the transceiver and the endpoint registers. The byte count buffer is loaded with the active transmit endpoints byte count value during transmit operations. This same buffer is used for receive transactions to count the number of bytes received and, upon the end of the transaction, transfer that number to the receive endpoints byte count register. When transmitting, the control logic handles parallel-to-serial conversion, CRC generation, NRZI encoding, and bit stuffing. When receiving, the control logic handles sync detection, packet identification, end-of-packet detection, bit (un)stuffing, NRZI decoding, CRC validation, and serial-to-parallel conversion. Errors detected by the control logic include bad CRC, timeout while waiting for EOP, and bit stuffing violations.
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11.8 I/O Registers
These I/O registers control and monitor USB operation: * * * * * * * USB address register (UADDR) USB control registers 0-4 (UCR0-UCR4) USB status registers 0-1 (USR0-USR1) USB interrupt registers 0-2 (UIR0-UIR2) USB endpoint 0 data registers 0-7 (UE0D0-UE0D7) USB endpoint 1 data registers 0-7 (UE1D0-UE1D7) USB endpoint 2 data registers 0-7 (UE2D0-UE2D7)
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Universal Serial Bus Module (USB)
11.8.1 USB Address Register
Address: $0038 Bit 7 Read: USBEN Write: Reset: 0* 0 0 0 0 0 0 0 UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 6 5 4 3 2 1 Bit 0
* USBEN bit is reset by POR or LVI reset only.
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Figure 11-15. USB Address Register (UADDR) USBEN -- USB Module Enable This read/write bit enables and disables the USB module and the USB pins. When USBEN is set, the USB module is enabled and the PTE4 interrupt is disabled. When USBEN is clear, the USB module will not respond to any tokens, USB reset and USB related interrupts are disabled, and pins PTE4/D- and PTE3/D+ function as high current open-drain I/O port pins PTE4 and PTE3. 1 = USB function enabled and PTE4 interrupt is disabled 0 = USB function disabled including USB interrupt, reset and reset interrupt UADD[6:0] -- USB Function Address These bits specify the USB address of the device. Reset clears these bits.
Technical Data 180 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Universal Serial Bus Module (USB) I/O Registers
11.8.2 USB Interrupt Register 0
Address: $0039 Bit 7 Read: EOPIE Write: Reset: 0 0 0 0 0 0 0 0 SUSPND TXD2IE RXD2IE TXD1IE 6 5 4 3 2 0 TXD0IE RXD0IE 1 Bit 0
= Unimplemented
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Figure 11-16. USB Interrupt Register 0 (UIR0) EOPIE -- End-of-Packet Detect Interrupt Enable This read/write bit enables the USB to generate CPU interrupt requests when the EOPF bit becomes set. Reset clears the EOPIE bit. 1 = End-of-packet sequence detection can generate a CPU interrupt request 0 = End-of-packet sequence detection cannot generate a CPU interrupt request SUSPND -- USB Suspend Bit To save power, this read/write bit should be set by the software if a 3ms constant idle state is detected on the USB bus. Setting this bit puts the transceiver into a power-saving mode. The RESUMF flag must be cleared before setting SUSPND. Software must clear this bit after the resume flag (RESUMF) is set while this resume interrupt flag is serviced. TXD2IE -- Endpoint 2 Transmit Interrupt Enable This read/write bit enables the transmit endpoint 2 to generate CPU interrupt requests when the TXD2F bit becomes set. Reset clears the TXD2IE bit. 1 = Transmit endpoint 2 can generate a CPU interrupt request 0 = Transmit endpoint 2 cannot generate a CPU interrupt request
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Universal Serial Bus Module (USB)
RXD2IE -- Endpoint 2 Receive Interrupt Enable This read/write bit enables the receive endpoint 2 to generate CPU interrupt requests when the RXD2F bit becomes set. Reset clears the RXD2IE bit. 1 = Receive endpoint 2 can generate a CPU interrupt request 0 = Receive endpoint 2 cannot generate a CPU interrupt request TXD1IE -- Endpoint 1 Transmit Interrupt Enable This read/write bit enables the transmit endpoint 1 to generate CPU interrupt requests when the TXD1F bit becomes set. Reset clears the TXD1IE bit. 1 = Transmit endpoints 1 can generate a CPU interrupt request 0 = Transmit endpoints 1 cannot generate a CPU interrupt request TXD0IE -- Endpoint 0 Transmit Interrupt Enable This read/write bit enables the transmit endpoint 0 to generate CPU interrupt requests when the TXD0F bit becomes set. Reset clears the TXD0IE bit. 1 = Transmit endpoint 0 can generate a CPU interrupt request 0 = Transmit endpoint 0 cannot generate a CPU interrupt request RXD0IE -- Endpoint 0 Receive Interrupt Enable This read/write bit enables the receive endpoint 0 to generate CPU interrupt requests when the RXD0F bit becomes set. Reset clears the RXD0IE bit. 1 = Receive endpoint 0 can generate a CPU interrupt request 0 = Receive endpoint 0 cannot generate a CPU interrupt request
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Technical Data 182
MC68HC908JG16 -- Rev. 1.0 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com MOTOROLA
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Universal Serial Bus Module (USB) I/O Registers
11.8.3 USB Interrupt Register 1
Address: $003A Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 EOPF 6 RSTF 5 TXD2F 4 RXD2F 3 TXD1F 2 RESUMF 1 TXD0F Bit 0 RXD0F
= Unimplemented
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Figure 11-17. USB Interrupt Register 1 (UIR1) EOPF -- End-of-Packet Detect Flag This read-only bit is set when a valid end-of-packet sequence is detected on the D+ and D- lines. Software must clear this flag by writing a logic 1 to the EOPFR bit. Reset clears this bit. Writing to EOPF has no effect. 1 = End-of-packet sequence has been detected 0 = End-of-packet sequence has not been detected RSTF -- USB Reset Flag This read-only bit is set when a valid reset signal state is detected on the D+ and D- lines. If the URSTD bit of the configuration register (CONFIG) is clear, this reset detection will generate an internal reset signal to reset the CPU and other peripherals including the USB module. If the URSTD bit is set, this reset detection will generate an USB interrupt. This bit is cleared by writing a logic 1 to the RSTFR bit. This bit also is cleared by a POR reset.
NOTE:
The USB bit in the SRSR (see 8.8.2 SIM Reset Status Register (SRSR)) is also a USB reset indicator. TXD2F -- Endpoint 2 Data Transmit Flag This read-only bit is set after the data stored in endpoint 2 transmit buffers has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD2FR bit.
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Universal Serial Bus Module (USB)
To enable the next data packet transmission, TX2E also must be set. If the TXD2F bit is not cleared, a NAK handshake will be returned in the next IN transaction. Reset clears this bit. Writing to TXD2F has no effect. 1 = Transmit on endpoint 2 has occurred 0 = Transmit on endpoint 2 has not occurred RXD2F -- Endpoint 2 Data Receive Flag This read-only bit is set after the USB module has received a data packet and responded with an ACK handshake packet. Software must clear this flag by writing a logic 1 to the RXD2FR bit after all of the received data has been read. Software also must set the RX2E bit to 1 to enable the next data packet reception. If the RXD2F bit is not cleared, a NAK handshake will be returned in the next OUT transaction. Reset clears this bit. Writing to RXD2F has no effect. 1 = Receive on endpoint 2 has occurred 0 = Receive on endpoint 2 has not occurred TXD1F -- Endpoint 1 Data Transmit Flag This read-only bit is set after the data stored in the endpoint 1 transmit buffer has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD1FR bit. To enable the next data packet transmission, TX1E also must be set. If the TXD1F bit is not cleared, a NAK handshake will be returned in the next IN transaction. Reset clears this bit. Writing to TXD1F has no effect. 1 = Transmit on endpoint 1has occurred 0 = Transmit on endpoint 1has not occurred RESUMF -- Resume Flag This read-only bit is set when USB bus activity is detected while the SUSPND bit is set. Software must clear this flag by writing a logic 1 to the RESUMFR bit. Reset clears this bit. Writing a logic 0 to RESUMF has no effect. 1 = USB bus activity has been detected 0 = No USB bus activity has been detected
Technical Data 184 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Universal Serial Bus Module (USB) I/O Registers
TXD0F -- Endpoint 0 Data Transmit Flag This read-only bit is set after the data stored in endpoint 0 transmit buffers has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD0FR bit. To enable the next data packet transmission, TX0E also must be set. If the TXD0F bit is not cleared, a NAK handshake will be returned in the next IN transaction.
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Reset clears this bit. Writing to TXD0F has no effect. 1 = Transmit on endpoint 0 has occurred 0 = Transmit on endpoint 0 has not occurred RXD0F -- Endpoint 0 Data Receive Flag This read-only bit is set after the USB module has received a data packet and responded with an ACK handshake packet. Software must clear this flag by writing a logic 1 to the RXD0FR bit after all of the received data has been read. Software also must set the RX0E bit to 1 to enable the next data packet reception. If the RXD0F bit is not cleared, the USB will respond with a NAK handshake to any endpoint 0 OUT tokens; but does not respond to a SETUP token. Reset clears this bit. Writing to RXD0F has no effect. 1 = Receive on endpoint 0 has occurred 0 = Receive on endpoint 0 has not occurred
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Universal Serial Bus Module (USB)
11.8.4 USB Interrupt Register 2
Address: $0018 Bit 7 Read: Write: Reset: 0 EOPFR 0 6 0 RSTFR 0 5 0 TXD2FR 0 4 0 RXD2FR 0 3 0 2 0 1 0 Bit 0 0 RXD0FR 0
TXD1FR RESUMFR TXD0FR 0 0 0
Figure 11-18. USB Interrupt Register 2 (UIR2)
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EOPFR -- End-of-Packet Flag Reset Writing a logic 1 to this write-only bit will clear the EOPF bit if it is set. Writing a logic 0 to the EOPFR has no effect. Reset clears this bit. RSTFR -- Clear Reset Indicator Bit Writing a logic 1 to this write-only bit will clear the RSTF bit if it is set. Writing a logic 0 to the RSTFR has no effect. Reset clears this bit. TXD2FR -- Endpoint 2 Transmit Flag Reset Writing a logic 1 to this write-only bit will clear the TXD2F bit if it is set. Writing a logic 0 to TXD2FR has no effect. Reset clears this bit. RXD2FR -- Endpoint 2 Receive Flag Reset Writing a logic 1 to this write-only bit will clear the RXD2F bit if it is set. Writing a logic 0 to RXD2FR has no effect. Reset clears this bit. TXD1FR -- Endpoint 1 Transmit Flag Reset Writing a logic 1 to this write-only bit will clear the TXD1F bit if it is set. Writing a logic 0 to TXD1FR has no effect. Reset clears this bit. RESUMFR -- Resume Flag Reset Writing a logic 1 to this write-only bit will clear the RESUMF bit if it is set. Writing to RESUMFR has no effect. Reset clears this bit. TXD0FR -- Endpoint 0 Transmit Flag Reset Writing a logic 1 to this write-only bit will clear the TXD0F bit if it is set. Writing a logic 0 to TXD0FR has no effect. Reset clears this bit. RXD0FR -- Endpoint 0 Receive Flag Reset Writing a logic 1 to this write-only bit will clear the RXD0F bit if it is set. Writing a logic 0 to RXD0FR has no effect. Reset clears this bit.
Technical Data 186 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) I/O Registers
11.8.5 USB Control Register 0
Address: $003B Bit 7 Read: T0SEQ Write: Reset: 0 0 0 0 0 0 0 0 6 0 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 5 4 3 2 1 Bit 0
Figure 11-19. USB Control Register 0 (UCR0)
Freescale Semiconductor, Inc...
T0SEQ -- Endpoint 0 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed at endpoint 0. Toggling of this bit must be controlled by software. Reset clears this bit. 1 = DATA1 token active for next endpoint 0 transmit 0 = DATA0 token active for next endpoint 0 transmit TX0E -- Endpoint 0 Transmit Enable This read/write bit enables a transmit to occur when the USB host controller sends an IN token to endpoint 0. Software should set this bit when data is ready to be transmitted. It must be cleared by software when no more endpoint 0 data needs to be transmitted. If this bit is 0 or the TXD0F is set, the USB will respond with a NAK handshake to any endpoint 0 IN tokens. Reset clears this bit. 1 = Data is ready to be sent 0 = Data is not ready. Respond with NAK RX0E -- Endpoint 0 Receive Enable This read/write bit enables a receive to occur when the USB host controller sends an OUT token to endpoint 0. Software should set this bit when data is ready to be received. It must be cleared by software when data cannot be received. If this bit is 0 or the RXD0F is set, the USB will respond with a NAK handshake to any endpoint 0 OUT tokens; but does not respond to a SETUP token. Reset clears this bit. 1 = Data is ready to be received 0 = Not ready for data. Respond with NAK
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com Technical Data 187
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB)
TP0SIZ3-TP0SIZ0 -- Endpoint 0 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for endpoint 0. These bits are cleared by reset.
11.8.6 USB Control Register 1
Address: $003C Bit 7 6 STALL1 0 5 TX1E 0 4 3 2 TP1SIZ2 0 1 TP1SIZ1 0 Bit 0 TP1SIZ0 0
Freescale Semiconductor, Inc...
Read: T1SEQ Write: Reset: 0 0 0 FRESUM TP1SIZ3
Figure 11-20. USB Control Register 1 (UCR1) T1SEQ -- Endpoint 1 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed to endpoint 1. Toggling of this bit must be controlled by software. Reset clears this bit. 1 = DATA1 token active for next endpoint 1 transmit 0 = DATA0 token active for next endpoint 1 transmit STALL1 -- Endpoint 1 Force Stall Bit This read/write bit causes endpoint 1 to return a STALL handshake when polled by either an IN or OUT token by the USB host controller. Reset clears this bit. 1 = Send STALL handshake 0 = Default TX1E -- Endpoint 1 Transmit Enable This read/write bit enables a transmit to occur when the USB host controller sends an IN token to endpoint 1. The appropriate endpoint enable bit, ENABLE1 bit in the UCR3 register, also should be set. Software should set the TX1E bit when data is ready to be transmitted. It must be cleared by software when no more data needs to be transmitted.
Technical Data 188 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) I/O Registers
If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake to any endpoint 1 directed IN tokens. Reset clears this bit. 1 = Data is ready to be sent 0 = Data is not ready. Respond with NAK FRESUM -- Force Resume This read/write bit forces a resume state (K or non-idle state) onto the USB data lines to initiate a remote wakeup. Software should control the timing of the forced resume to be between 10 and 15 ms. Setting this bit will not cause the RESUMF bit to be set. 1 = Force data lines to K state 0 = Default TP1SIZ3-TP1SIZ0 -- Endpoint 1 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for endpoint 1. These bits are cleared by reset.
Freescale Semiconductor, Inc...
11.8.7 USB Control Register 2
Address: $0019 Bit 7 Read: T2SEQ Write: Reset: 0 0 0 0 0 0 0 0 STALL2 TX2E RX2E TP2SIZ3 TP2SIZ2 TP2SIZ1 TP2SIZ0 6 5 4 3 2 1 Bit 0
Figure 11-21. USB Control Register 2 (UCR2) T2SEQ -- Endpoint 2 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed to endpoint 2. Toggling of this bit must be controlled by software. Reset clears this bit. 1 = DATA1 token active for next endpoint 2 transmit 0 = DATA0 token active for next endpoint 2 transmit
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
Technical Data 189
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB)
STALL2 -- Endpoint 2 Force Stall Bit This read/write bit causes endpoint 2 to return a STALL handshake when polled by either an IN or OUT token by the USB host controller. Reset clears this bit. 1 = Send STALL handshake 0 = Default TX2E -- Endpoint 2 Transmit Enable This read/write bit enables a transmit to occur when the USB host controller sends an IN token to endpoint 2. The appropriate endpoint enable bit, ENABLE2 bit in the UCR3 register, also should be set. Software should set the TX2E bit when data is ready to be transmitted. It must be cleared by software when no more data needs to be transmitted. If this bit is 0 or the TXD2F is set, the USB will respond with a NAK handshake to any endpoint 2 directed IN tokens. Reset clears this bit. 1 = Data is ready to be sent 0 = Data is not ready. Respond with NAK RX2E -- Endpoint 2 Receive Enable This read/write bit enables a receive to occur when the USB host controller sends an OUT token to endpoint 2. Software should set this bit when data is ready to be received. It must be cleared by software when data cannot be received. If this bit is 0 or the RXD2F is set, the USB will respond with a NAK handshake to any endpoint 2 OUT tokens. Reset clears this bit. 1 = Data is ready to be received 0 = Not ready for data. Respond with NAK TP2SIZ3-TP2SIZ0 -- Endpoint 2 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for endpoint 2. These bits are cleared by reset.
Freescale Semiconductor, Inc...
Technical Data 190
MC68HC908JG16 -- Rev. 1.0 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) I/O Registers
11.8.8 USB Control Register 3
Address: $001A Bit 7 Read: Write: Reset: 0 TX1ST 6 0 OSTALL0 ISTALL0 TX1STR 0 0 0 0 0* 0 0 5 4 3 0 PULLEN ENABLE2 ENABLE1 2 1 Bit 0
= Unimplemented
Freescale Semiconductor, Inc...
* PULLEN bit is reset by POR or LVI reset only.
Figure 11-22. USB Control Register 3 (UCR3) TX1ST -- Endpoint 0 Transmit First Flag This read-only bit is set if the endpoint 0 data transmit flag (TXD0F) is set when the USB control logic is setting the endpoint 0 data receive flag (RXD0F). In other words, if an unserviced endpoint 0 transmit flag is still set at the end of an endpoint 0 reception, then this bit will be set. This bit lets the firmware know that the endpoint 0 transmission happened before the endpoint 0 reception. Reset clears this bit. 1 = IN transaction occurred before SETUP/OUT 0 = IN transaction occurred after SETUP/OUT TX1STR -- Clear Endpoint 0 Transmit First Flag Writing a logic 1 to this write-only bit will clear the TX1ST bit if it is set. Writing a logic 0 to the TX1STR has no effect. Reset clears this bit. OSTALL0 -- Endpoint 0 Force STALL Bit for OUT token This read/write bit causes endpoint 0 to return a STALL handshake when polled by an OUT token by the USB host controller. The USB hardware clears this bit when a SETUP token is received. Reset clears this bit. 1 = Send STALL handshake 0 = Default
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
Technical Data 191
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB)
ISTALL0 -- Endpoint 0 Force STALL Bit for IN token This read/write bit causes endpoint 0 to return a STALL handshake when polled by an IN token by the USB host controller. The USB hardware clears this bit when a SETUP token is received. Reset clears this bit. 1 = Send STALL handshake 0 = Default PULLEN -- Pull-up Enable
Freescale Semiconductor, Inc...
This read/write bit controls the pull-up option for the USB D- pin if the USB module is enabled. 1 = Configure D- pin to have internal pull-up 0 = Disconnect D- pin internal pull-up ENABLE2 -- Endpoint 2 Enable This read/write bit enables endpoint 2 and allows the USB to respond to IN or OUT packets addressed to endpoint 2. Reset clears this bit. 1 = Endpoint 2 is enabled and can respond to an IN or OUT token 0 = Endpoint 2 is disabled ENABLE1 -- Endpoint 1 Enable This read/write bit enables endpoint 1 and allows the USB to respond to IN packets addressed to endpoint 1. Reset clears this bit. 1 = Endpoint 1 is enabled and can respond to an IN token 0 = Endpoint 1 is disabled
Technical Data 192 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) I/O Registers
11.8.9 USB Control Register 4 USB control register 4 directly controls the USB data pins D+ and D-. If the FUSBO bit, and the USBEN bit of the USB address register (UADDR) are set, the output buffers of the USB modules are enabled and the corresponding levels of the USB data pins D+ and D- are equal to the values set by the FDP and the FDM bits.
Address: $001B Bit 7 6 0 5 0 4 0 3 0 FUSBO Write: Reset: 0 0 0 0 0 0 0 0 FDP FDM 2 1 Bit 0
Freescale Semiconductor, Inc...
Read:
0
= Unimplemented
Figure 11-23. USB Control Register 4 (UCR4) FUSBO -- Force USB Output This read/write bit enables the USB output buffers. 1 = Enables USB output buffers 0 = USB module in normal operation FDP -- Force D+ This read/write bit determinates the output level of D+. 1 = D+ at output high level 0 = D+ at output low level FDM -- Force D- This read/write bit determinates the output level of D-. 1 = D- at output high level 0 = D- at output low level
NOTE:
Customers must be very careful when setting the UCR4 register. When the FUSBO and the USBEN bits are set, the USB module is in output mode and it will not recognize any USB signals including the USB reset signal. The UCR4 register is used for some special applications. Customers are not normally expected to use this register.
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
Technical Data 193
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB)
11.8.10 USB Status Register 0
Address: $003D Bit 7 Read: Write: Reset: = Unimplemented Unaffected by reset R0SEQ 6 SETUP 5 0 4 0 3 RP0SIZ3 2 RP0SIZ2 1 RP0SIZ1 Bit 0 RP0SIZ0
Freescale Semiconductor, Inc...
Figure 11-24. USB Status Register 0 (USR0) R0SEQ -- Endpoint 0 Receive Sequence Bit This read-only bit indicates the type of data packet last received for endpoint 0 (DATA0 or DATA1). 1 = DATA1 token received in last endpoint 0 receive 0 = DATA0 token received in last endpoint 0 receive SETUP -- SETUP Token Detect Bit This read-only bit indicates that a valid SETUP token has been received. 1 = Last token received for endpoint 0 was a SETUP token 0 = Last token received for endpoint 0 was not a SETUP token RP0SIZ3-RP0SIZ0 -- Endpoint 0 Receive Data Packet Size These read-only bits store the number of data bytes received for the last OUT or SETUP transaction for endpoint 0.
Technical Data 194 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) I/O Registers
11.8.11 USB Status Register 1
Address: $003E Bit 7 Read: Write: Reset: U 0 0 0 U U U U R2SEQ 6 TXACK 5 TXNAK 4 TXSTL 3 RP2SIZ3 2 RP2SIZ2 1 RP2SIZ1 Bit 0 RP2SIZ0
= Unimplemented
U = Unaffected by reset
Freescale Semiconductor, Inc...
Figure 11-25. USB Status Register 2 (USR1) R2SEQ -- Endpoint 2 Receive Sequence Bit This read-only bit indicates the type of data packet last received for endpoint 2 (DATA0 or DATA1). 1 = DATA1 token received in last endpoint 2 receive 0 = DATA0 token received in last endpoint 2 receive TXACK -- ACK Token Transmit Bit This read-only bit indicates that an ACK token has been transmitted. This bit is updated at the end of the data transmission. 1 = Last token transmitted for endpoint 0 was an ACK token 0 = Last token transmitted for endpoint 0 was not an ACK token TXNAK -- NAK Token Transmit Bit This read-only bit indicates that a TXNAK token has been transmitted. This bit is updated at the end of the data transmission. 1 = Last token transmitted for endpoint 0 was a NAK token 0 = Last token transmitted for endpoint 0 was not a NAK token TXSTL -- STALL Token Transmit Bit This read-only bit indicates that a STALL token has been transmitted. This bit is updated at the end of the data transmission. 1 = Last token transmitted for endpoint 0 was a STALL token 0 = Last token transmitted for endpoint 0 was not a STALL token RP2SIZ3-RP2SIZ0 -- Endpoint 2 Receive Data Packet Size These read-only bits store the number of data bytes received for the last OUT transaction for endpoint 2.
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com Technical Data 195
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB)
11.8.12 USB Endpoint 0 Data Registers
Address: $0020 Bit 7 Read: UE0R07 Write: UE0T07 Reset: UE0D0 6 UE0R06 UE0T06 5 UE0R05 UE0T05 4 UE0R04 UE0T04 3 UE0R03 UE0T03 2 UE0R02 UE0T02 1 UE0R01 UE0T01 Bit 0 UE0R00 UE0T00
Unaffected by reset
Freescale Semiconductor, Inc...
UE0D7 UE0R76 UE0T76 UE0R75 UE0T75 UE0R74 UE0T74 UE0R73 UE0T73 UE0R72 UE0T72 UE0R71 UE0T71 UE0R70 UE0T70
Address:
$0027
Read: UE0R77 Write: UE0T77 Reset:
Unaffected by reset
Figure 11-26. USB Endpoint 0 Data Registers (UE0D0-UE0D7) UE0Rx7-UE0Rx0 -- Endpoint 0 Receive Data Buffer These read-only bits are serially loaded with OUT token or SETUP token data directed at endpoint 0. The data is received over the USB's D+ and D- pins. UE0Tx7-UE0Tx0 -- Endpoint 0 Transmit Data Buffer These write-only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at endpoint 0.
Technical Data 196 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) I/O Registers
11.8.13 USB Endpoint 1 Data Registers
Address: $0028 Bit 7 Read: Write: UE1T07 Reset: UE1T06 UE1T05 UE1T04 UE1T03 UE1T02 UE1T01 UE1T00 UE1D0 6 5 4 3 2 1 Bit 0
Unaffected by reset
Freescale Semiconductor, Inc...
UE1D7
Address: Read:
$002F
Write: UE1T77 Reset:
UE1T76
UE1T75
UE1T74
UE1T73
UE1T72
UE1T71
UE1T70
Unaffected by reset = Unimplemented
Figure 11-27. USB Endpoint 1 Data Registers (UE1D0-UE1D7) UE1Tx7-UE1Tx0 -- Endpoint 1 Transmit or Receive Data Buffer These write-only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at endpoint 1.
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
Technical Data 197
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB)
11.8.14 USB Endpoint 2 Data Registers
Address: $0030 Bit 7 Read: UE2R07 Write: UE2T07 Reset: UE2D0 6 UE2R06 UE2T06 5 UE2R05 UE2T05 4 UE2R04 UE2T04 3 UE2R03 UE2T03 2 UE2R02 UE2T02 1 UE2R01 UE2T01 Bit 0 UE2R00 UE2T00
Unaffected by reset
Freescale Semiconductor, Inc...
UE2D7 UE2R76 UE2T76 UE2R75 UE2T75 UE2R74 UE2T74 UE2R73 UE2T73 UE2R72 UE2T72 UE2R71 UE2T71 UE2R70 UE2T70
Address:
$0037
Read: UE2R77 Write: UE2T77 Reset:
Unaffected by reset
Figure 11-28. USB Endpoint 2 Data Registers (UE2D0-UE2D7) UE2Rx7-UE2Rx0 -- Endpoint 2 Receive Data Buffer These read-only bits are serially loaded with OUT token data directed at endpoint 2. The data is received over the USB's D+ and D- pins. UE2Tx7-UE2Tx0 -- Endpoint 2 Transmit Data Buffer These write-only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at endpoint 2.
Technical Data 198 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) USB Interrupts
11.9 USB Interrupts
The USB module is capable of generating interrupts and causing the CPU to execute the USB interrupt service routine. There are three types of USB interrupts: * * End-of-transaction interrupts signify either a completed transaction receive or transmit transaction. Resume interrupts signify that the USB bus is reactivated after having been suspended. End-of-packet interrupts signify that a low-speed end-of-packet signal was detected.
Freescale Semiconductor, Inc...
*
All USB interrupts share the same interrupt vector. Firmware is responsible for determining which interrupt is active.
11.9.1 USB End-of-Transaction Interrupt There are five possible end-of-transaction interrupts: * * Endpoint 0 or 2 receive Endpoint 0, 1 or 2 transmit
End-of-transaction interrupts occur as detailed in the following sections.
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
Technical Data 199
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB)
11.9.1.1 Receive Control Endpoint 0 For a control OUT transaction directed at endpoint 0, the USB module will generate an interrupt by setting the RXD0F flag in the UIR0 register. The conditions necessary for the interrupt to occur are shown in the flowchart in Figure 11-29.
VALID OUT TOKEN RECEIVED FOR ENDPOINT 0
Freescale Semiconductor, Inc...
Y VALID DATA TOKEN RECEIVED FOR ENDPOINT 0? Y USB MODULE ENABLED? (USBEN = 1) Y ENDPOINT 0 RECEIVE NOT STALLED? (OSTALL0 = 0) Y ENDPOINT 0 RECEIVE READY TO RECEIVE? (RX0E = 1) AND (RXD0F = 0) Y ACCEPT DATA SET/CLEAR R0SEQ BIT N SEND NAK HANDSHAKE N SEND STALL HANDSHAKE N NO RESPONSE FROM USB FUNCTION N TIMEOUT NO RESPONSE FROM USB FUNCTION
ERROR FREE DATA PACKET? Y SET RXD0F TO 1
N
IGNORE TRANSACTION NO RESPONSE FROM USB FUNCTION
RECEIVE CONTROL ENDPOINT INTERRUPT ENABLED? (RXD0IE = 1) Y VALID TRANSACTION INTERRUPT GENERATED
N
NO INTERRUPT
Figure 11-29. OUT Token Data Flow for Receive Endpoint 0
Technical Data 200 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) USB Interrupts
SETUP transactions cannot be stalled by the USB function. A SETUP received by a control endpoint will clear the ISTALL0 and OSTALL0 bits. The conditions for receiving a SETUP interrupt are shown in Figure 11-30.
VALID SETUP TOKEN RECEIVED FOR ENDPOINT 0? Y USB MODULE ENABLED? (USBEN = 1) Y ENDPOINT 0 RECEIVE READY TO RECEIVE? (RX0E = 1) AND (RXD0F = 0) Y N NO RESPONSE FROM USB FUNCTION N NO RESPONSE FROM USB FUNCTION
Freescale Semiconductor, Inc...
ACCEPT DATA SET/CLEAR R0SEQ BIT SET SETUP BIT TO 1
ERROR FREE DATA PACKET? Y SET RXD0F TO 1
N
IGNORE TRANSACTION NO RESPONSE FROM USB FUNCTION
RECEIVE CONTROL ENDPOINT INTERRUPT ENABLED? (RXD0IE = 1) Y VALID TRANSACTION INTERRUPT GENERATED
N
NO INTERRUPT
Figure 11-30. SETUP Token Data Flow for Receive Endpoint 0
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
Technical Data 201
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB)
11.9.1.2 Transmit Control Endpoint 0 For a control IN transaction directed at endpoint 0, the USB module will generate an interrupt by setting the TXD0F flag in the UIR1 register. The conditions necessary for the interrupt to occur are shown in the flowchart in Figure 11-31.
VALID IN TOKEN RECEIVED FOR ENDPOINT 0
Freescale Semiconductor, Inc...
Y USB MODULE ENABLED? (USBEN = 1) Y TRANSMIT ENDPOINT NOT STALLED BY FIRMWARE (ISTALL0 = 0)? Y TRANSMIT ENDPOINT READY TO TRANSFER? (TX0E = 1) AND (TXD0F = 0) Y SEND DATA DATA PID SET BY T0SEQ N SEND NAK HANDSHAKE N SEND STALL HANDSHAKE N NO RESPONSE FROM USB FUNCTION
ACK RECEIVED AND NO TIMEOUT CONDITION OCCURS? Y SET TXD0F TO 1
N
NO RESPONSE FROM USB FUNCTION
TRANSMIT ENDPOINT INTERRUPT ENABLED? (TXD0IE = 1) Y VALID TRANSACTION INTERRUPT GENERATED
N
NO INTERRUPT
Figure 11-31. IN Token Data Flow for Transmit Endpoint 0
Technical Data 202 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB) USB Interrupts
11.9.1.3 Transmit Endpoint 1 For an IN transaction directed at endpoint 1, the USB module will generate an interrupt by setting the TXD1F in the UIR1 register. The conditions necessary for the interrupt to occur are shown in Figure 11-32.
VALID IN TOKEN RECEIVED FOR ENDPOINT 1
Freescale Semiconductor, Inc...
Y USB MODULE ENABLED? (USBEN = 1) Y TRANSMIT ENDPOINT NOT STALLED BY FIRMWARE (STALL1 = 1)? Y TRANSMIT ENDPOINT READY TO TRANSFER? (TX1E = 1) AND (TXD1F = 0) AND (UE1TR = 0) Y TRANSMIT ENDPOINT ENABLED? (ENABLE = 1) Y SEND DATA DATA PID SET BY T1SEQ N NO RESPONSE FROM USB FUNCTION N SEND NAK HANDSHAKE N SEND STALL HANDSHAKE N NO RESPONSE FROM USB FUNCTION
ACK RECEIVED AND NO TIMEOUT CONDITION OCCURS? Y SET TXD1F TO 1
N
NO RESPONSE FROM USB FUNCTION
TRANSMIT ENDPOINT INTERRUPT ENABLED? (TXD1IE = 1) Y VALID TRANSACTION INTERRUPT GENERATED
N
NO INTERRUPT
Figure 11-32. IN Token Data Flow for Transmit Endpoint 1
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
Technical Data 203
Freescale Semiconductor, Inc.
Universal Serial Bus Module (USB)
11.9.1.4 Transmit Endpoint 2 For an IN transaction directed at endpoint 2, the USB module will generate an interrupt by setting the TXD2F in the UIR1 register. 11.9.1.5 Receive Endpoint 2 For an OUT transaction directed at endpoint 2, the USB module will generate an interrupt by setting the RXD2F in the UIR1 register.
Freescale Semiconductor, Inc...
11.9.2 Resume Interrupt The USB module will generate a CPU interrupt if low-speed bus activity is detected after entering the suspend state. A transition of the USB data lines to the non-idle state (K state) while in the suspend mode will set the RESUMF flag in the UIR1 register. There is no interrupt enable bit for this interrupt source and an interrupt will be executed if the I-bit in the CCR is cleared. A resume interrupt can only occur while the MCU is in the suspend mode.
11.9.3 End-of-Packet Interrupt The USB module can generate a USB interrupt upon detection of an end-of-packet signal for low-speed devices. Upon detection of an endof-packet signal, the USB module sets the EOPF bit and will generate a CPU interrupt if the EOPIE bit in the UIR0 register is set.
Technical Data 204 Universal Serial Bus Module (USB) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Technical Data -- MC68HC908JG16
Section 12. Serial Communications Interface Module (SCI)
12.1 Contents
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
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12.3 12.4
12.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 12.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 12.5.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.5.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.5.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.5.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.5.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . . 215 12.5.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 215 12.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12.5.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 12.5.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 12.5.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12.5.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 12.5.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 12.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . . 226
12.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.8.1 TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
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Serial Communications Interface
12.8.2 RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
12.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 12.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 12.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 12.9.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 12.9.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 12.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 12.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
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12.2 Introduction
This section describes the serial communications interface (SCI) module, which allows high-speed asynchronous communications with peripheral devices and other MCUs.
NOTE:
References to DMA (direct-memory access) and associated functions are only valid if the MCU has a DMA module. This MCU does not have the DMA function. Any DMA-related register bits should be left in their reset state for normal MCU operation.
12.3 Features
Features of the SCI module include the following: * * * * * * * * Full-duplex operation Standard mark/space non-return-to-zero (NRZ) format 32 programmable baud rates Programmable 8-bit or 9-bit character length Separately enabled transmitter and receiver Separate receiver and transmitter CPU interrupt requests Programmable transmitter output polarity Baud rate clock source is OSCDCLK (2 x OSCXCLK)
Technical Data 206 Serial Communications Interface Module (SCI) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Serial Communications Interface Module (SCI) Features
*
Two receiver wakeup methods: - Idle line wakeup - Address mark wakeup
*
Interrupt-driven operation with eight interrupt flags: - Transmitter empty - Transmission complete - Receiver full
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- Idle receiver input - Receiver overrun - Noise error - Framing error - Parity error * * * Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection
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Serial Communications Interface 12.4 Pin Name Conventions
The generic names of the SCI I/O pins are: * * RxD (receive data) TxD (transmit data)
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SCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full name of an SCI input or output reflects the name of the shared port pin. Table 12-1 shows the full names and the generic names of the SCI I/O pins. The generic pin names appear in the text of this section. Table 12-1. Pin Name Conventions
Generic Pin Names: Full Pin Names: RxD PTC1/RxD TxD PTC0/TxD
12.5 Functional Description
Figure 12-1 shows the structure of the SCI module. The SCI allows fullduplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. The baud rate clock source for the SCI is the OSCDCLK from the oscillator circuit, which is two times the crystal clock, OSCXCLK.
Technical Data 208 Serial Communications Interface Module (SCI) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Serial Communications Interface Module (SCI) Functional Description
INTERNAL BUS
SCI DATA REGISTER TRANSMITTER INTERRUPT CONTROL RECEIVER INTERRUPT CONTROL DMA INTERRUPT CONTROL ERROR INTERRUPT CONTROL
SCI DATA REGISTER TRANSMIT SHIFT REGISTER
RxD
RECEIVE SHIFT REGISTER
TxD
TXINV SCTIE
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TCIE SCRIE ILIE TE RE RWU SBK SCTE TC SCRF IDLE OR NF FE PE LOOPS LOOPS WAKEUP CONTROL RECEIVE CONTROL FLAG CONTROL M WAKE ILTY OSCDCLK /3 PRESCALER BAUD DIVIDER PEN PTY DATA SELECTION CONTROL ENSCI
R8 T8
DMARE DMATE
ORIE NEIE FEIE PEIE
TRANSMIT CONTROL
ENSCI
BKF RPF
/ 16
Figure 12-1. SCI Module Block Diagram
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Technical Data 209
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Serial Communications Interface
Addr.
Register Name
Bit 7
6 ENSCI 0 TCIE 0 T8
5 TXINV 0 SCRIE 0 DMARE 0 SCRF
4 M 0 ILIE 0 DMATE 0 IDLE
3 WAKE 0 TE 0 ORIE 0 OR
2 ILTY 0 RE 0 NEIE 0 NF
1 PEN 0 RWU 0 FEIE 0 FE
Bit 0 PTY 0 SBK 0 PEIE 0 PE
$005A
Read: LOOPS SCI Control Register 1 Write: (SCC1) Reset: 0 Read: SCI Control Register 2 Write: (SCC2) Reset: Read: SCI Control Register 3 Write: (SCC3) Reset: Read: SCI Status Register 1 Write: (SCS1) Reset: Read: SCI Status Register 2 Write: (SCS2) Reset: Read: SCI Data Register Write: (SCDR) Reset: Read: SCI Baud Rate Register Write: (SCBR) Reset: SCTIE 0 R8
$005B
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$005C
U SCTE
U TC
$005D
1
1
0
0
0
0
0 BKF
0 RPF
$005E
0 R7 T7
0 R6 T6
0 R5 T5
0 R4 T4
0 R3 T3
0 R2 T2
0 R1 T1
0 R0 T0
$005F
Unaffected by reset 0 0 SCP1 0 0 0 SCP0 0 R = Reserved R SCR2 0 U = Unaffected SCR1 0 SCR0 0
$0060
= Unimplemented
Figure 12-2. SCI I/O Register Summary
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Serial Communications Interface Module (SCI) Functional Description
12.5.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 12-3.
8-BIT DATA FORMAT BIT M IN SCC1 CLEAR START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6
PARITY BIT BIT 7 STOP BIT
NEXT START BIT
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9-BIT DATA FORMAT BIT M IN SCC1 SET START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
PARITY BIT BIT 8 STOP BIT
NEXT START BIT
Figure 12-3. SCI Data Formats
12.5.2 Transmitter Figure 12-4 shows the structure of the SCI transmitter. The baud rate clock source for the SCI is the OSCDCLK.
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Technical Data 211
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Serial Communications Interface
INTERNAL BUS
OSCDCLK
/3
PRESCALER
BAUD DIVIDER
/ 16
SCI DATA REGISTER
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SCP0 SCR1 SCR2 SCR0 TRANSMITTER CPU INTERRUPT REQUEST TRANSMITTER DMA SERVICE REQUEST TXINV
H
8 MSB
7
6
5
4
3
2
1
0
START L
SCP1 STOP
11-BIT TRANSMIT SHIFT REGISTER
TxD
M SHIFT ENABLE PEN PTY PARITY GENERATION LOAD FROM SCDR
PREAMBLE ALL 1s
T8 DMATE DMATE SCTIE SCTE DMATE SCTE SCTIE TC TCIE
TRANSMITTER CONTROL LOGIC
SCTE
LOOPS SCTIE TC TCIE ENSCI TE
Figure 12-4. SCI Transmitter
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BREAK ALL 0s SBK
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Serial Communications Interface Module (SCI) Functional Description
12.5.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). 12.5.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the TxD pin. The SCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To initiate an SCI transmission: 1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1). 2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in SCI control register 2 (SCC2). 3. Clear the SCI transmitter empty bit by first reading SCI status register 1 (SCS1) and then writing to the SCDR. 4. Repeat step 3 for each subsequent transmission. At the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter CPU interrupt request. When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port pin.
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Serial Communications Interface
12.5.2.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has these effects on SCI registers: * * * * * * Sets the framing error bit (FE) in SCS1 Sets the SCI receiver full bit (SCRF) in SCS1 Clears the SCI data register (SCDR) Clears the R8 bit in SCC3 Sets the break flag bit (BKF) in SCS2 May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits
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12.5.2.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted.
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Serial Communications Interface Module (SCI) Functional Description
NOTE:
When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin. Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost. Toggle the TE bit for a queued idle character when the SCTE bit becomes set and just before writing the next byte to the SCDR.
12.5.2.5 Inversion of Transmitted Output
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The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at logic 1. (See 12.9.1 SCI Control Register 1.) 12.5.2.6 Transmitter Interrupts These conditions can generate CPU interrupt requests from the SCI transmitter: * SCI transmitter empty (SCTE) -- The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate transmitter CPU interrupt requests. Transmission complete (TC) -- The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests.
*
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Serial Communications Interface
12.5.3 Receiver Figure 12-5 shows the structure of the SCI receiver. 12.5.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). 12.5.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request.
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Technical Data 216 Serial Communications Interface Module (SCI) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Serial Communications Interface Module (SCI) Functional Description
INTERNAL BUS
SCR1 SCP1 SCP0 OSCDCLK /3 PRESCALER BAUD DIVIDER SCR2 SCR0 / 16 DATA RECOVERY ALL 0s ALL 1s MSB SCI DATA REGISTER
11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 0
RxD
H
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BKF RPF ERROR CPU INTERRUPT REQUEST DMA SERVICE REQUEST
CPU INTERRUPT REQUEST
M WAKE ILTY PEN PTY WAKEUP LOGIC PARITY CHECKING IDLE ILIE DMARE SCRF SCRIE DMARE SCRF SCRIE DMARE OR ORIE NF NEIE FE FEIE PE PEIE
SCRF IDLE
R8
ILIE
SCRIE
DMARE OR ORIE NF NEIE FE FEIE PE PEIE
Figure 12-5. SCI Receiver Block Diagram
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Technical Data 217
START L RWU
STOP
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Serial Communications Interface
12.5.3.3 Data Sampling The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at the following times (see Figure 12-6): * * After every start bit After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0)
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To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
START BIT RxD
LSB
SAMPLES
START BIT QUALIFICATION
START BIT VERIFICATION
DATA SAMPLING
RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT4 RT CLOCK STATE RT CLOCK RESET RT16
Figure 12-6. Receiver Data Sampling
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Serial Communications Interface Module (SCI) Functional Description
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 12-2 summarizes the results of the start bit verification samples. Table 12-2. Start Bit Verification
RT3, RT5, and RT7 Samples 000 001 Start Bit Verification Yes Yes Yes No Yes No No No Noise Flag 0 1 1 0 1 0 0 0
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010 011 100 101 110 111
Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 12-3 summarizes the results of the data bit samples. Table 12-3. Data Bit Recovery
RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0
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Serial Communications Interface
NOTE:
The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 12-4 summarizes the results of the stop bit samples. Table 12-4. Stop Bit Recovery
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RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111
Framing Error Flag 1 1 1 0 1 0 0 0
Noise Flag 0 1 1 1 1 1 1 0
12.5.3.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. 12.5.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate
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Serial Communications Interface Module (SCI) Functional Description
tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. Slow Data Tolerance
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Figure 12-7 shows how much a slow received character can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10.
MSB
STOP
RT10
RT11
RT12
RT13
RT14
RT15
DATA SAMPLES
Figure 12-7. Slow Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 12-7, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times x 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is 154 - 147 x 100 = 4.54% ------------------------154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles.
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Technical Data 221
RT16
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RECEIVER RT CLOCK
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Serial Communications Interface
With the misaligned character shown in Figure 12-7, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 170 - 163 x 100 = 4.12% ------------------------170 Fast Data Tolerance Figure 12-8 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10.
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STOP
IDLE OR NEXT CHARACTER
RT10
RT11
RT12
RT13
RT14
RT15
DATA SAMPLES
Figure 12-8. Fast Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 12-8, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles = 160 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is * 154 - 160 x 100 = 3.90% ------------------------154
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RT16
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RECEIVER RT CLOCK
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Serial Communications Interface Module (SCI) Functional Description
For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 12-8, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is
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170 - 176 x 100 = 3.53% ------------------------170
12.5.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled. Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state: * Address mark -- An address mark is a logic 1 in the most significant bit position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can then compare the character containing the address mark to the user-defined address of the receiver. If they are the same, the receiver remains awake and processes the characters that follow. If they are not the same, software can set the RWU bit and put the receiver back into the standby state. Idle input line condition -- When the WAKE bit is clear, an idle character on the RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver does not set the receiver idle bit, IDLE, or the SCI receiver
*
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Serial Communications Interface
full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit.
NOTE:
With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle may cause the receiver to wake up immediately.
12.5.3.7 Receiver Interrupts The following sources can generate CPU interrupt requests from the SCI receiver: * SCI receiver full (SCRF) -- The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU interrupts. Idle input (IDLE) -- The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in from the RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate CPU interrupt requests.
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*
12.5.3.8 Error Interrupts The following receiver error flags in SCS1 can generate CPU interrupt requests: * Receiver overrun (OR) -- The OR bit indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR. The previous character remains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI error CPU interrupt requests. Noise flag (NF) -- The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU interrupt requests.
*
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MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Serial Communications Interface Module (SCI) Low-Power Modes
*
Framing error (FE) -- The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU interrupt requests. Parity error (PE) -- The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests.
*
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12.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 12.6.1 Wait Mode The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. Refer to 8.7 Low-Power Modes for information on exiting wait mode. 12.6.2 Stop Mode The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect SCI register states. SCI module operation resumes after an external interrupt. Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data. Refer to 8.7 Low-Power Modes for information on exiting stop mode.
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Technical Data 225
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Serial Communications Interface 12.7 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state.
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To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit.
12.8 I/O Signals
Port C shares two of its pins with the SCI module. The two SCI I/O pins are: * * 12.8.1 TxD (Transmit Data) The PTC0/TxD pin is the serial data output from the SCI transmitter. The SCI shares the PTC0/TxD pin with port C. When the SCI is enabled, the PTC0/TxD pin is an output regardless of the state of the DDRC0 bit in data direction register C (DDRC). 12.8.2 RxD (Receive Data) The PTC1/RxD pin is the serial data input to the SCI receiver. The SCI shares the PTC1/RxD pin with port C. When the SCI is enabled, the PTC1/RxD pin is an input regardless of the state of the DDRC1 bit in data direction register C (DDRC).
Technical Data 226 Serial Communications Interface Module (SCI) For More Information On This Product, Go to: www.freescale.com MC68HC908JG16 -- Rev. 1.0 MOTOROLA
PTC0/TxD -- Transmit data PTC1/RxD -- Receive data
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Serial Communications Interface Module (SCI) I/O Registers
12.9 I/O Registers
These I/O registers control and monitor SCI operation: * * * * SCI control register 1 (SCC1) SCI control register 2 (SCC2) SCI control register 3 (SCC3) SCI status register 1 (SCS1) SCI status register 2 (SCS2) SCI data register (SCDR) SCI baud rate register (SCBR)
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* * *
12.9.1 SCI Control Register 1 SCI control register 1: * * * * * * * * Enables loop mode operation Enables the SCI Controls output polarity Controls character length Controls SCI wakeup method Controls idle character detection Enables parity function Controls parity type
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Technical Data 227
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Serial Communications Interface
Address:
$005A Bit 7 6 ENSCI 0 5 TXINV 0 4 M 0 3 WAKE 0 2 ILTY 0 1 PEN 0 Bit 0 PTY 0
Read: LOOPS Write: Reset: 0
Figure 12-9. SCI Control Register 1 (SCC1) LOOPS -- Loop Mode Select Bit
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This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit. 1 = Loop mode enabled 0 = Normal operation enabled ENSCI -- Enable SCI Bit This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. 1 = SCI enabled 0 = SCI disabled TXINV -- Transmit Inversion Bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted
NOTE:
Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits.
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MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Serial Communications Interface Module (SCI) I/O Registers
M -- Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 12-5.) The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters WAKE -- Wakeup Condition Bit
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This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the RxD pin. Reset clears the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup ILTY -- Idle Line Type Bit This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. Reset clears the ILTY bit. 1 = Idle character bit count begins after stop bit 0 = Idle character bit count begins after start bit PEN -- Parity Enable Bit This read/write bit enables the SCI parity function. (See Table 12-5.) When enabled, the parity function inserts a parity bit in the most significant bit position. (See Figure 12-3.) Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled
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Serial Communications Interface
PTY -- Parity Bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity. (See Table 12-5.) Reset clears the PTY bit. 1 = Odd parity 0 = Even parity
NOTE:
Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Table 12-5. Character Format Selection
Control Bits M 0 1 0 0 1 1 PEN and PTY 0X 0X 10 11 10 11 Start Bits 1 1 1 1 1 1 Data Bits 8 9 7 7 8 8 Character Format Parity None None Even Odd Even Odd Stop Bits 1 1 1 1 1 1 Character Length 10 bits 11 bits 10 bits 10 bits 11 bits 11 bits
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12.9.2 SCI Control Register 2 SCI control register 2: * Enables the following CPU interrupt requests: - Enables the SCTE bit to generate transmitter CPU interrupt requests - Enables the TC bit to generate transmitter CPU interrupt requests - Enables the SCRF bit to generate receiver CPU interrupt requests - Enables the IDLE bit to generate receiver CPU interrupt requests
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MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Serial Communications Interface Module (SCI) I/O Registers
* * * *
Address:
Enables the transmitter Enables the receiver Enables SCI wakeup Transmits SCI break characters
$005B Bit 7 6 TCIE 0 5 SCRIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 Bit 0 SBK 0
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Read: SCTIE Write: Reset: 0
Figure 12-10. SCI Control Register 2 (SCC2) SCTIE -- SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset clears the SCTIE bit. 1 = SCTE enabled to generate CPU interrupt 0 = SCTE not enabled to generate CPU interrupt TCIE -- Transmission Complete Interrupt Enable Bit This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears the TCIE bit. 1 = TC enabled to generate CPU interrupt requests 0 = TC not enabled to generate CPU interrupt requests SCRIE -- SCI Receive Interrupt Enable Bit This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Reset clears the SCRIE bit. 1 = SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt ILIE -- Idle Line Interrupt Enable Bit This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests
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Serial Communications Interface
TE -- Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the TxD returns to the idle condition (logic 1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit. 1 = Transmitter enabled 0 = Transmitter disabled
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NOTE:
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RE -- Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled
NOTE:
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RWU -- Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation
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MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Serial Communications Interface Module (SCI) I/O Registers
SBK -- Send Break Bit Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no logic 1s between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted
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NOTE:
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble.
12.9.3 SCI Control Register 3 SCI control register 3: * * Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted Enables these interrupts: - Receiver overrun interrupts - Noise error interrupts - Framing error interrupts *
Address:
Parity error interrupts
$005C Bit 7 6 T8 5 DMARE 0 4 DMATE 0 3 ORIE 0 U = Unaffected 2 NEIE 0 1 FEIE 0 Bit 0 PEIE 0
Read: Write: Reset:
R8
U
U
= Unimplemented
Figure 12-11. SCI Control Register 3 (SCC3)
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Serial Communications Interface
R8 -- Received Bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other 8 bits. When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 -- Transmitted Bit 8 When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset has no effect on the T8 bit. DMARE -- DMA Receive Enable Bit
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CAUTION:
The DMA module is not included on this MCU. Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance. 1 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI receiver CPU interrupt requests enabled) 0 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI receiver CPU interrupt requests enabled) DMATE -- DMA Transfer Enable Bit
CAUTION:
The DMA module is not included on this MCU. Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance. 1 = SCTE DMA service requests enabled; SCTE CPU interrupt requests disabled 0 = SCTE DMA service requests disabled; SCTE CPU interrupt requests enabled
Technical Data 234 Serial Communications Interface Module (SCI) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Serial Communications Interface Module (SCI) I/O Registers
ORIE -- Receiver Overrun Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR. 1 = SCI error CPU interrupt requests from OR bit enabled 0 = SCI error CPU interrupt requests from OR bit disabled NEIE -- Receiver Noise Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE. 1 = SCI error CPU interrupt requests from NE bit enabled 0 = SCI error CPU interrupt requests from NE bit disabled FEIE -- Receiver Framing Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE. 1 = SCI error CPU interrupt requests from FE bit enabled 0 = SCI error CPU interrupt requests from FE bit disabled PEIE -- Receiver Parity Error Interrupt Enable Bit This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE. (See 12.9.4 SCI Status Register 1.) Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled
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Technical Data 235
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Serial Communications Interface
12.9.4 SCI Status Register 1 SCI status register 1 (SCS1) contains flags to signal these conditions: * * * * * Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data to SCDR complete Receiver input idle Receiver overrun Noisy data Framing error Parity error
$005D Bit 7 Read: Write: Reset: 1 1 0 0 0 0 0 0 SCTE 6 TC 5 SCRF 4 IDLE 3 OR 2 NF 1 FE Bit 0 PE
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* * *
Address:
= Unimplemented
Figure 12-12. SCI Status Register 1 (SCS1) SCTE -- SCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register
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MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Serial Communications Interface Module (SCI) I/O Registers
TC -- Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is automatically cleared when data, preamble or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress SCRF -- SCI Receiver Full Bit This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF. 1 = Received data available in SCDR 0 = Data not available in SCDR IDLE -- Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an SCI error CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) OR -- Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIE
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Serial Communications Interface Module (SCI) For More Information On This Product, Go to: www.freescale.com Technical Data 237
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Serial Communications Interface
bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing sequence. Figure 12-13 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flagclearing sequence reads byte 3 in the SCDR instead of byte 2. In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flagclearing routine can check the OR bit in a second read of SCS1 after reading the data register. NF -- Receiver Noise Flag Bit This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected FE -- Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected
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Technical Data 238
MC68HC908JG16 -- Rev. 1.0 Serial Communications Interface Module (SCI) For More Information On This Product, Go to: www.freescale.com MOTOROLA
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Serial Communications Interface Module (SCI) I/O Registers
NORMAL FLAG CLEARING SEQUENCE SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = 1 OR = 1 READ SCDR BYTE 3 SCRF = 0 OR = 0
BYTE 1 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1
BYTE 2 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 2
BYTE 3
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DELAYED FLAG CLEARING SEQUENCE SCRF = 1 OR = 1 SCRF = 0 OR = 1 SCRF = 1 SCRF = 1 OR = 1 BYTE 3
BYTE 1
BYTE 2 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1
Figure 12-13. Flag Clearing Sequence
PE -- Receiver Parity Error Bit This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates a PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected
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Serial Communications Interface
12.9.5 SCI Status Register 2 SCI status register 2 contains flags to signal the following conditions: * *
Address:
Break character detected Incoming data
$005E Bit 7 6 5 4 3 2 1 BKF Bit 0 RPF
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Read: Write: Reset: 0 0 0 0 0 0
0
0
= Unimplemented
Figure 12-14. SCI Status Register 2 (SCS2) BKF -- Break Flag Bit This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading the SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the RxD pin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected RPF -- Reception in Progress Flag Bit This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress
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Serial Communications Interface Module (SCI) I/O Registers
12.9.6 SCI Data Register The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit shift registers.
Address: $005F Bit 7 Read: Write: R7 T7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0
Freescale Semiconductor, Inc...
Reset:
Unaffected by reset
Figure 12-15. SCI Data Register (SCDR) R7/T7-R0/T0 -- Receive/Transmit Data Bits Reading the SCI data register accesses the read-only received data bits, R7:R0. Writing to the SCI data register writes the data to be transmitted, T7:T0. Reset has no effect on the SCI data register.
NOTE:
Do not use read/modify/write instructions on the SCI data register.
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Serial Communications Interface
12.9.7 SCI Baud Rate Register The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter.
Address: $0060 Bit 7 Read: Write: 0 6 0 SCP1 SCP0 0 R R SCR2 0 = Reserved SCR1 0 SCR0 0 5 4 3 2 1 Bit 0
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Reset:
0
0
0
= Unimplemented
Figure 12-16. SCI Baud Rate Register (SCBR) SCP1 and SCP0 -- SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 12-6. Reset clears SCP1 and SCP0. Table 12-6. SCI Baud Rate Prescaling
SCP1 and SCP0 00 01 10 11 Prescaler Divisor (PD) 1 3 4 13
SCR2-SCR0 -- SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 12-7. Reset clears SCR2-SCR0.
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MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Serial Communications Interface Module (SCI) I/O Registers
Table 12-7. SCI Baud Rate Selection
SCR2, SCR1, and SCR0 000 001 010 011 100 Baud Rate Divisor (BD) 1 2 4 8 16 32 64 128
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101 110 111
Use this formula to calculate the SCI baud rate: SCI clock source baud rate = -------------------------------------------48 x PD x BD where: SCI clock source = OSCDCLK PD = prescaler divisor BD = baud rate divisor
Table 12-8 shows the SCI baud rates that can be generated with a 24MHz OSCDCLK (OSCXCLK=12MHz) as SCI clock source.
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Serial Communications Interface
Table 12-8. SCI Baud Rate Selection Examples
SCP1 and SCP0 00 00 00 00 00 00 Prescaler Divisor (PD) 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 SCR2, SCR1, and SCR0 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 38461.54 19230.77 9615.38 4807.69 2403.85 1201.92 600.96 300.48 Baud rate settings not recommended Baud Rate (OSCDCLK=24MHz)
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00 00 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11
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Technical Data -- MC68HC908JG16
Section 13. Analog-to-Digital Converter (ADC)
13.1 Contents
13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
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13.3
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 13.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 13.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.7.1 ADC Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . 250 13.7.2 ADC Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . 250 13.7.3 ADC Voltage Reference High Pin (VREFH). . . . . . . . . . . . . 250 13.7.4 ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . 250 13.7.5 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 251 13.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 253
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Analog-to-Digital Converter (ADC) 13.2 Introduction
This section describes the analog-to-digital converter (ADC). The ADC is a 8-channel 8-bit successive approximation ADC.
13.3 Features
Features of the ADC module include:
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* * * * *
Addr. Register Name Read: ADC Status and Control Register Write: (ADSCR) Reset: Read: $0062 ADC Data Register Write: (ADR) Reset: Read: $0063 ADC Input Clock Register Write: (ADICLK) Reset:
Eight channels with multiplexed input Linear successive approximation 8-bit resolution Single or continuous conversion Conversion complete flag or conversion complete interrupt
Bit 7 COCO 0 AD7 6 AIEN 0 AD6 5 ADCO 0 AD5 4 ADCH4 1 AD4 3 ADCH3 1 AD3 2 ADCH2 1 AD2 1 ADCH1 1 AD1 Bit 0 ADCH0 1 AD0
$0061
Indeterminate after reset 0 ADIV2 0 ADIV1 0 ADIV0 0 0 0 0 0 0 0 0 0 0
= Unimplemented
Figure 13-1. ADC I/O Register Summary
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Analog-to-Digital Converter (ADC) Functional Description
13.4 Functional Description
Eight ADC channels are available for sampling external sources at pins PTA7-PTA0. An analog multiplexer allows the single ADC converter to select one of the eight ADC channels as ADC voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. The ADC resolution is eight bits. When the conversion is completed, ADC puts the result in the ADC data register and sets a flag or generates an interrupt. Figure 13-2 shows a block diagram of the ADC.
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INTERNAL DATA BUS READ DDRA WRITE DDRA RESET WRITE PTA PTAx DDRAx DISABLE
PTAx/KBAx/ADx
READ PTA
ADC DATA REGISTER
DISABLE
ADC CHANNEL x
CONVERSION INTERRUPT COMPLETE LOGIC
ADC
ADC VOLTAGE IN ADCVIN
CHANNEL SELECT (1 OF 8 CHANNELS)
ADCH[4:0]
AIEN
COCO
ADC CLOCK CLOCK GENERATOR
BUS CLOCK
ADIV[2:0]
Figure 13-2. ADC Block Diagram
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Analog-to-Digital Converter (ADC)
13.4.1 ADC Port I/O Pins PTA7-PTA0 are general-purpose I/O pins that are shared with the ADC channels. The channel select bits, ADCH[4:0], in the ADC status and control register define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read.
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13.4.2 Voltage Conversion When the input voltage to the ADC equals to VREFH, the ADC converts the signal to $FF (full scale). If the input voltage equals to VREFL, the ADC converts it to $00. Input voltages between VREFH and VREFL is a straight-line linear conversion. All other input voltages will result in $FF if greater than VREFH and $00 if less than VREFL.
NOTE:
Input voltage should not exceed the analog supply voltages.
13.4.3 Conversion Time Conversion starts after a write to the ADSCR. One conversion will take between 16 and 17 ADC clock cycles, therefore: Conversion time = 16 to17 ADC cycles ADC frequency
Number of bus cycles = conversion time x bus frequency For example: with a 6MHz bus clock and divide-by-4 prescaler, the ADC clock is 1.5MHz, then one conversion will take 10.67s to complete.
NOTE:
The ADC frequency must be between tADIC minimum and tADIC maximum to meet ADC specifications. (See 20.13 ADC Electrical Characteristics.)
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Analog-to-Digital Converter (ADC) Interrupts
13.4.4 Continuous Conversion In the continuous conversion mode, the ADC continuously converts the selected channel filling the ADC data register with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The conversion complete bit, COCO, in the ADC status and control register is set after each conversion and can be cleared by writing to the ADC status and control register or reading of the ADC data register.
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13.4.5 Accuracy and Precision The conversion process is monotonic and has no missing codes.
13.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled. The interrupt vector is defined in Table 2-1 . Vector Addresses.
13.6 Low-Power Modes
The WAIT and STOP instructions can put the MCU in low-power consumption standby modes.
13.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits in the ADC status and control register to logic 1's before executing the WAIT instruction.
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Analog-to-Digital Converter (ADC)
13.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode.
13.7 I/O Signals
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The ADC module has eight channels that are shared with port A I/O pins, PTA7/KBA7/AD7-PTA0/KBA0/AD0. 13.7.1 ADC Analog Power Pin (VDDA) The ADC analog portion uses VDDA as its power pin. Connect the VDDA pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDA for good results.
NOTE:
Route VDDA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package.
13.7.2 ADC Analog Ground Pin (VSSA) The ADC analog portion uses VSSA as its ground pin. Connect the VSSA pin to the same voltage potential as VSS. 13.7.3 ADC Voltage Reference High Pin (VREFH) VREFH is the high voltage reference for the ADC. 13.7.4 ADC Voltage Reference Low Pin (VREFL) VREFL is the low voltage reference for the ADC. 13.7.5 ADC Voltage In (ADCVIN) ADCVIN is the input voltage signal from one of the eight ADC channels to the ADC module.
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Analog-to-Digital Converter (ADC) I/O Registers
13.8 I/O Registers
Three I/O registers control and monitor ADC operation: * * * ADC status and control register (ADSCR) ADC data register (ADR) ADC input clock register (ADICLK)
13.8.1 ADC Status and Control Register
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Function of the ADC status and control register is described here.
Address: $0061 Bit 7 Read: COCO Write: Reset: 0 0 0 1 1 1 1 1 AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 6 5 4 3 2 1 Bit 0
= Unimplemented
Figure 13-3. ADC Status and Control Register (ADSCR) COCO -- Conversions Complete Bit When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever the ADC status and control register is written, or whenever the ADC data register is read. Reset clears this bit. If the AIEN bit is a logic 1, the COCO becomes a read/write bit, which should be cleared to logic 0 for CPU to service the ADC interrupt request. Reset clears this bit. 1 = conversion completed (AIEN = 0) 0 = conversion not completed (AIEN = 0) AIEN -- ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status and control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled
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Analog-to-Digital Converter (ADC)
ADCO -- ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion ADCH[4:0] -- ADC Channel Select Bits ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels or reference voltages. The five channel select bits are detailed in the Table 13-1.
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NOTE:
Care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. Recovery from the disabled state requires one conversion cycle to stabilize. Table 13-1. MUX Channel Select
NOTE:
ADCH4 0 0 0 0 0 0 0 0 0 1 1 1 1
ADCH3 0 0 0 0 0 0 0 0 1 1 1 1 1
ADCH2 0 0 0 0 1 1 1 1 0 1 1 1 1
ADCH1 0 0 1 1 0 0 1 1 0 0 0 1 1
ADCH0 0 1 0 1 0 1 0 1 0 0 1 0 1
ADC Channel ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
Input Select PTA0/KBA0/AD0 PTA1/KBA1/AD1 PTA2/KBA2/AD2 PTA3/KBA3/AD3 PTA4/KBA4/AD4 PTA5/KBA5/AD5 PTA6/KBA6/AD6 PTA7/KBA7/AD7 Unused(1)
--
-- --
VREFH VREFHL ADC power off
Notes: 1. If any unused channels are selected, the resulting ADC conversion will be unknown.
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Analog-to-Digital Converter (ADC) I/O Registers
13.8.2 ADC Data Register One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC conversion completes.
Address: $0062 Bit 7 Read: Write: AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 Bit 0 AD0
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Reset: = Unimplemented
Indeterminate after reset
Figure 13-4. ADC Data Register (ADR)
13.8.3 ADC Input Clock Register The ADC input clock register (ADICLK) selects the clock frequency for the ADC.
Address: $0063 Bit 7 Read: ADIV2 Write: Reset: 0 0 0 0 0 0 0 0 ADIV1 ADIV0 6 5 4 0 3 0 2 0 1 0 Bit 0 0
= Unimplemented
Figure 13-5. ADC Input Clock Register (ADICLK) ADIV[2:0] -- ADC Clock Prescaler Bits ADIV[2:0] form a 3-bit field which selects the divider used by the ADC to generate the internal ADC clock. Table 13-2 shows the available clock configurations. The ADC clock should be set to approximately 1.5MHz.
NOTE:
The ADC frequency must be between tADIC minimum and tADIC maximum to meet ADC specifications. (See 20.13 ADC Electrical Characteristics.)
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Analog-to-Digital Converter (ADC)
Table 13-2. ADC Clock Divider
ADIV2 0 0 0 0 1 ADIV1 0 0 1 1 X ADIV0 0 1 0 1 X ADC Clock Rate Bus Clock / 1 Bus Clock / 2 Bus Clock / 4 Bus Clock / 8 Bus Clock / 16
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X = don't care
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Technical Data -- MC68HC908JG16
Section 14. Input/Output (I/O) Ports
14.1 Contents
14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
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14.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 14.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 14.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . 259 14.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 14.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 14.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . 261 14.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14.5.2 Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . 264 14.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 14.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . 267 14.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.7.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . . 271 14.8 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 14.8.1 Port Option Control Register . . . . . . . . . . . . . . . . . . . . . . . 273
14.2 Introduction
Twenty (20) bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or outputs.
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Input/Output (I/O) Ports
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage.
Bit 7 PTA7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
Addr. $0000
Register Name Read: Port A Data Register Write: (PTA) Reset: Read: Port B Data Register Write: (PTB) Reset: Read: Port C Data Register Write: (PTC) Reset: Read: Port D Data Register Write: (PTD) Reset:
Unaffected by reset 0 0 0 0 0 0 0 PTB0
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$0001
Unaffected by reset 0 0 0 0 0 0 PTC1 PTC0
$0002
Unaffected by reset 0 0 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
$0003
Unaffected by reset DDRA6 0 0 0 0 0 0 0 0 DDRA5 0 0 0 0 0 DDRD5 0 0 DDRA4 0 0 0 0 0 DDRD4 0 PTE4 DDRA3 0 0 0 0 0 DDRD3 0 PTE3 DDRA2 0 0 0 0 0 DDRD2 0 PTE2 DDRA1 0 0 0 DDRC1 0 DDRD1 0 PTE1 DDRA0 0
Read: DDRA7 Data Direction Register A $0004 Write: (DDRA) Reset: 0* * DDRA7 bit is reset by POR or LVI reset only. Read: Data Direction Register B $0005 Write: (DDRB) Reset: Read: Data Direction Register C $0006 Write: (DDRC) Reset: Read: Data Direction Register D $0007 Write: (DDRD) Reset: $0008 Read: Port E Data Register Write: (PTE) Reset: 0 0 0 0 0 0 0
DDRB0 0 DDRC0 0 DDRD0 0 PTE0
Unaffected by reset = Unimplemented
Figure 14-1. I/O Port Register Summary
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Input/Output (I/O) Ports Introduction
Addr.
Register Name
Bit 7 0 0
6 0 0
5 0 0
4 DDRE4 0 PTE4P 0
3 DDRE3 0 PTE3P 0
2 DDRE2 0 PCP 0
1 DDRE1 0 PBP 0
Bit 0 DDRE0 0 PAP 0
Read: Data Direction Register E $0009 Write: (DDRE) Reset: $001D
Read: Port Option Control PTE20P Register Write: (POCR) Reset: 0
PTDLDD PTDILDD 0 0
= Unimplemented
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Figure 14-1. I/O Port Register Summary Table 14-1. Port Control Register Bits Summary
Module Control Port Bit 0 1 2 3 A 4 5 6 7 B C 1 D 0-3 0 DDRC1 DDRD[0:3] DDRE0 -- TIM1 or TIM2 TIM1 0 0 DDRA4 DDRA5 DDRA6 DDRA7 DDRB0 DDRC0 SCI -- -- SCC1 $005A -- T1SC $000A or T2SC $0040 T1SC0 $0010 or T1SC1 $0013 T2SC0 $0046 or T2SC1 $0049 UADDR $0038 -- ENSCI PTC1/RxD -- PS[2:0] ELS0B:ELS0A or ELS1B:ELS1A ELS0B:ELS0A or ELS1B:ELS1A USBEN PTE4/D- PTD0-PTD3 PTE0/TCLK KBI KBIER $0017 KBIE[7:0] PTA4/KBA4/AD4 PTA5/KBA5/AD5 PTA6/KBA6/AD6 PTA7/KBA7/AD7 PTB0 PTC0/TxD DDR Module DDRA0 DDRA1 DDRA2 DDRA3 ADC ADSCR(1) $0061 ADCH[4:0] Register Control Bit PTA0/KBA0/AD0 PTA1/KBA1/AD1 PTA2/KBA2/AD2 PTA3/KBA3/AD3 Pin
1 E 2 3 4
DDRE1
PTE1/T1CH01
DDRE2 DDRE3
TIM2
PTE2/T2CH01 PTE3/D+
USB DDRE4 Notes: 1. Register has the highest priority control on port pin.
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Input/Output (I/O) Ports 14.3 Port A
Port A is an 8-bit general-purpose bidirectional I/O port with software configurable pullups, and shares its pins with the keyboard interrupt module (KBI) and analog-to-digital converter module (ADC).
14.3.1 Port A Data Register The port A data register contains a data latch for each of the eight port A pins.
Address: $0000 Bit 7 Read: PTA7 Write: Reset:
Alternative
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6 PTA6
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
Unaffected by reset KBA7 AD7 KBA6 AD6 Optional pullup KBA5 AD5 Optional pullup KBA4 AD4 Optional pullup KBA3 AD3 Optional pullup KBA2 AD2 Optional pullup KBA1 AD1 Optional pullup KBA0 AD0 Optional pullup
Function:
Alternative
Function:
Additional Optional Function: pullup
Figure 14-2. Port A Data Register (PTA) PTA[7:0] -- Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. The port A pullup control bit, PAP, in the port option control register (POCR) enables pullups on port A pins if the respective pin is configured as an input. (See 14.8 Port Options.) KBA7-KBA0 -- Keyboard Interrupts The keyboard interrupt enable bits, KBIE7-KBIE0, in the keyboard interrupt enable register (KBIER), enable the port A pins as external interrupt pins. (See Section 16. Keyboard Interrupt Module (KBI).)
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Input/Output (I/O) Ports Port A
AD7-AD0 -- Analog-to-Digital Input Pins AD7-AD0 are pins used for the input channels to the analog-to-digital converter module. The channel select bits, ADCH[4:0], in the ADC status and control register (ADSCR) define which port A pin will be used as an ADC input and overrides any control from the port I/O or keyboard interrupt logic. (See Section 13. Analog-to-Digital Converter (ADC).)
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14.3.2 Data Direction Register A Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.
Address: $0004 Bit 7 Read: DDRA7 Write: Reset: 0* 0 0 0 0 0 0 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 6 5 4 3 2 1 Bit 0
* DDRA7 bit is reset by POR or LVI reset only.
Figure 14-3. Data Direction Register A (DDRA) DDRA[7:0] -- Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 14-4 shows the port A I/O logic.
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Input/Output (I/O) Ports
READ DDRA ($0004)
WRITE DDRA ($0004) INTERNAL DATA BUS RESET WRITE PTA ($0000) PTAx PTAx DDRAx
READ PTA ($0000)
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Figure 14-4. Port A I/O Circuit When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 14-2 summarizes the operation of the port A pins. Table 14-2. Port A Pin Functions
DDRA Bit 0 1 PTA Bit I/O Pin Mode Accesses to DDRA Read/Write X(1) X Input, Hi-Z(2) Output DDRA[7:0] DDRA[7:0] Accesses to PTA Read Pin PTA[7:0] Write PTA[7:0](3) PTA[7:0]
Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input.
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Input/Output (I/O) Ports Port B
14.4 Port B
Port B is an 1-bit general-purpose bidirectional I/O port with software configurable pullup. 14.4.1 Port B Data Register The port B data register contains the data latch for PTB0.
Address: $0001 Bit 7 Read: Write: Reset: Unaffected by reset 0 6 0 5 0 4 0 3 0 2 0 1 0 PTB0 Bit 0
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Figure 14-5. Port B Data Register (PTB) PTB0 -- PTB0 Data Bit This read/write bit is software programmable. Data direction of PTB0 pin is under control of the DDRB0 bit in the data direction register B. Reset has no effect on port B data. The port B pullup control bit, PBP, in the port option control register (POCR) enables the pullup on PTB0 pin if configured as an input. (See 14.8 Port Options.) 14.4.2 Data Direction Register B Data direction register B determines whether PTB0 is an input or an output. Writing a logic 1 to DDRB0 bit enables the output buffer for the PTB0 pin; a logic 0 disables the output buffer.
Address: $0005 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 DDRB0 Bit 0
Figure 14-6. Data Direction Register B (DDRB)
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DDRB0 -- Data Direction Register B Bit This read/write bit control PTB0 data direction. Reset clears DDRB0, configuring PTB0 pin as input. 1 = PTB0 pin configured as output 0 = PTB0 pin configured as input
NOTE:
Avoid glitches on PTB0 pin by writing to the port B data register before changing data direction register B bit from 0 to 1. Figure 14-7 shows the port B I/O circuit logic.
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READ DDRB ($0005)
WRITE DDRB ($0005) INTERNAL DATA BUS RESET WRITE PTB ($0001) PTB0 PTB0 DDRB0
READ PTB ($0001)
Figure 14-7. Port B I/O Circuit When bit DDRB0 is a logic 1, reading address $0001 reads the PTB0 data latch. When bit DDRB0 is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 14-3 summarizes the operation of the PTB0 pin. Table 14-3. Port B Pin Functions
DDRB0 Bit 0 1 PTB0 Bit I/O Pin Mode Accesses to DDRB Read/Write X(1) X Input, Hi-Z(2) Output DDRB0 DDRB0 Accesses to PTB Read Pin PTB0 Write PTB0(3) PTB0
Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input.
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Input/Output (I/O) Ports Port C
14.5 Port C
Port C is a 2-bit special function port that shares its pins with the serial communications interface (SCI) module. These pins have software configurable pullups.
14.5.1 Port C Data Register The port C data register contains a data latch for each of the two port C pins.
Address: $0002 Bit 7 Read: Write: Reset:
Alternative
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6 0
5 0
4 0
3 0
2 0
1 PTC1
Bit 0 PTC0
0
Unaffected by reset RxD Optional pullup TxD Optional pullup
Function: Additional Function:
Figure 14-8. Port C Data Register (PTC) PTC[1:0] -- Port C Data Bits These read/write bits are software-programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data. The port C pullup enable bit, PCP, in the port option control register (POCR) enables pullups on PTC[1:0] if the respective pin is configured as an input. (See 14.8 Port Options.) TxD, RxD -- SCI Data I/O Pins The TxD and RxD pins are the transmit data output and receive data input for the SCI module. The SCI enable bit, ENSCI, in the SCI control register 1 enables the PTC0/TxD and PTC1/RxD pins as SCI TxD and RxD pins and overrides any control from the port I/O. See Section 12. Serial Communications Interface Module (SCI).
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14.5.2 Data Direction Register C Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer.
Address: $0006 Bit 7 Read: 0 6 0 5 0 4 0 3 0 2 0 DDRC1 DDRC0 0 1 Bit 0
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Write: Reset: 0 0 0 0 0 0 0
Figure 14-9. Data Direction Register C (DDRC) DDRC[1:0] -- Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC[1:0], configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input
NOTE:
Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 14-10 shows the port C I/O logic.
READ DDRC ($0006)
WRITE DDRC ($0006) INTERNAL DATA BUS RESET WRITE PTC ($0002) PTCx PTCx DDRCx
READ PTC ($0002)
Figure 14-10. Port C I/O Circuit
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Input/Output (I/O) Ports Port C
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 14-4 summarizes the operation of the port C pins. Table 14-4. Port C Pin Functions
DDRC Bit PTC Bit I/O Pin Mode Accesses to DDRC Read/Write 0 1 X(1) X Input, Hi-Z(2) Output DDRC[1:0] DDRC[1:0] Accesses to PTC Read Pin PTC[1:0] Write PTC[1:0](3) PTC[1:0]
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Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input.
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Input/Output (I/O) Ports 14.6 Port D
Port D is an 4-bit general-purpose bidirectional I/O port. These pins are open-drain when configured as output.
14.6.1 Port D Data Register The port D data register contains a data latch for each of the four port D pins.
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NOTE:
Bits 5-4 of PTD are not available in the 32-pin low-profile quad flat pack.
Address: $0003 Bit 7 Read: Write: Reset: Additional Function: 10mA sink Unaffected by reset 10mA sink 10mA sink 10mA sink 25mA sink 25mA sink 0 6 0 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 5 4 3 2 1 Bit 0
Figure 14-11. Port D Data Register (PTD) PTD[5:0] -- Port D Data Bits These read/write bits are software programmable. Data direction of each port D pin is under control of the corresponding bit in data direction register D. Reset has no effect on port D data. The LED direct drive bit, PTDLDD, in the port option control register (POCR) controls the drive options for PTD5-PTD2 pins. The infrared LED drive bit, PTDILDD, in the POCR controls the drive options for PTD1-PTD0 pins. (See 14.8 Port Options.)
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Input/Output (I/O) Ports Port D
14.6.2 Data Direction Register D Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
Address: $0007 Bit 7 Read: 0 6 0 DDRD5 DDRD4 0 DDRD3 0 DDRD2 0 DDRD1 0 DDRD0 0 5 4 3 2 1 Bit 0
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Write: Reset: 0 0 0
Figure 14-12. Data Direction Register D (DDRD) DDRD[5:0] -- Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD[5:0], configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input Port D pins are open-drain when configured as output.
NOTE: NOTE:
Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. For those devices packaged in a 32-pin low-profile quad flat pack, PTD5-4 are not connected. DDRD5-4 should be set to a 1 to configure PTD5-4 as outputs. Figure 14-13 shows the port D I/O circuit logic.
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Input/Output (I/O) Ports
READ DDRD ($0007)
WRITE DDRD ($0007) INTERNAL DATA BUS RESET WRITE PTD ($0003) PTDx PTDx DDRDx
READ PTD ($0003)
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Figure 14-13. Port D I/O Circuit When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 14-5 summarizes the operation of the port D pins. Table 14-5. Port D Pin Functions
DDRD Bit 0 1 PTD Bit I/O Pin Mode Accesses to DDRD Read/Write X(1) X Input, Hi-Z(2) Output DDRD[5:0] DDRD[5:0] Accesses to PTD Read Pin PTD[5:0] Write PTD[5:0](3) PTD[5:0]
Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input.
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Input/Output (I/O) Ports Port E
14.7 Port E
Port E is a 5-bit special function port that shares three of its pins with the timer interface modules (TIMs) and two of its pins with the USB data pins D+ and D-. PTE4 and PTE3 are open-drain when configured as output. 14.7.1 Port E Data Register The port E data register contains a data latch for each of the five port E pins.
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Address:
$0008 Bit 7 6 0 5 0 PTE4 PTE3 PTE2 PTE1 PTE0 4 3 2 1 Bit 0
Read: Write: Reset:
Alternative
0
Unaffected by reset D- Optional pullup External interrupt
Open-drain Open-drain
Function: Additional Function: Additional Function:
D+ Optional pullup
T2CH01 Optional pullup
T1CH01 Optional pullup
TCLK Optional pullup
= Unimplemented
Figure 14-14. Port E Data Register (PTE) PTE[4:0] -- Port E Data Bits PTE[4:0] are read/write, software-programmable bits. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. The PTE4 and PTE3 pullup enable bits, PTE4P and PTE3P, in the port option control register (POCR) enable 5k pullups on PTE4 and PTE3 if the respective pin is configured as an input and the USB module is disabled. (See 14.8 Port Options.)
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Input/Output (I/O) Ports
The PTE[2:0] pullup enable bit, PTE20P, in the port option control register (POCR) enables pullups on PTE2-PTE0, regardless of the pin is configured as an input or an output. (See 14.8 Port Options.) PTE4 pin functions as an external interrupt when PTE4IE=1 in the IRQ option control register (IOCR) and USBEN=0 in the USB address register (USB disabled). (See 15.9 IRQ Option Control Register.) D- and D+ -- USB Data Pins D- and D+ are the differential data lines used by the USB module. (See Section 11. Universal Serial Bus Module (USB).) The USB module enable bit, USBEN, in the USB address register (UADDR) controls the pin options for PTE4/D- and PTE3/D+. When the USB module is enabled, PTE4/D- and PTE3/D+ function as USB data pins D- and D+. When the USB module is disabled, PTE4/D- and PTE3/D+ function as 10mA open-drain high current pins for PS/2 clock and data use. The pullup enable bit, PULLEN, in the USB control register 3 (UCR3) enables a 1.5k pullup on D- pin when the USB module is enabled. (See 11.8.8 USB Control Register 3.)
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NOTE:
PTE4/D- pin has two programmable pullup resistors. One is used for PTE4 when the USB module is disabled and another is used for D- when the USB module is enabled. T2CH01 and T1CH01 -- Timer Channel I/O Bits The PTE2/T2CH01 and PTE1/T1CH01 pins are the respective TIM2 and TIM1 input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether the PTE2/T2CH01 and PTE1/T1CH01 pins are timer channel I/O pins or general-purpose I/O pins. (See Section 10. Timer Interface Module (TIM).) TCLK -- Timer Clock Input The PTE0/TCLK pin is the external clock input for TIM1 and TIM2. The prescaler select bits, PS[2:0], select PTE0/TCLK as the TIM clock input. When not selected as the TIM clock, PTE0/TCLK is available for general purpose I/O. (See Section 10. Timer Interface Module (TIM).)
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Input/Output (I/O) Ports Port E
NOTE:
Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the TIM. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins.
14.7.2 Data Direction Register E Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer.
Address: $0009 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 4 3 2 1 Bit 0
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= Unimplemented
Figure 14-15. Data Direction Register E (DDRE) DDRE[4:0] -- Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE[4:0], configuring all port E pins as inputs. 1 = Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input
NOTE:
Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1. Figure 14-16 shows the port E I/O circuit logic.
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Input/Output (I/O) Ports
READ DDRE ($0009)
WRITE DDRE ($0009) INTERNAL DATA BUS RESET WRITE PTE ($0008) PTEx PTEx DDREx
READ PTE ($0008)
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Figure 14-16. Port E I/O Circuit When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 14-4 summarizes the operation of the port E pins. Table 14-6. Port E Pin Functions
DDRE Bit 0 1 PTE Bit X(1) X I/O Pin Mode Accesses to DDRE Read/Write Input, Hi-Z(2) Output DDRE[4:0] DDRE[4:0] Accesses to PTE Read Pin PTE[4:0] Write PTE[4:0](3) PTE[4:0]
Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input.
14.8 Port Options
All pins of port A, port B, port C, and port E have programmable pullup resistors. Port D has programmable LED drive capability; PTD5-PTD2 each have 10mA high current sink, and PTD1-PTD0 each have 25mA high current sink.
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Input/Output (I/O) Ports Port Options
14.8.1 Port Option Control Register The port option control register controls the pullup options for port A, port B, port C, and port E pins. It also controls the drive configuration on port D.
Address: $001D Bit 7 Read: PTE20P PTDLDD PTDILDD 0 0 PTE4P 0 PTE3P 0 PCP 0 PBP 0 PAP 0 6 5 4 3 2 1 Bit 0
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Write: Reset: 0
Figure 14-17. Port Option Control Register (POCR) PTE20P -- Pins PTE[2:0] Pullup Enable This read/write bit controls the pullup option for the PTE2-PTE0 pins, regardless whether the pins are configured as input or output. 1 = Configure PTE2-PTE0 to have internal pullups 0 = Disconnect PTE2-PTE0 internal pullups PTDLDD -- LED Direct Drive Control This read/write bit controls the output current capability of PTD5-PTD2 pins. When set, each port pin has 10mA current sink limit. An LED can be connected directly between the pin and VDD without the need of a series resistor. 1 = PTD5-PTD2 configured for direct LED drive capability; when a pin is set as an output, the pin is an open-drain pin with 10mA current sink limit 0 = PTD5-PTD2 configured as standard I/O port pins PTDILDD -- Infrared LED Drive Control This read/write bit controls the output current capability of PTD1 and PTD0 pins. When set, each port pin has 25mA current sink capability. An infrared LED can be connected directly between the pin and VDD. 1 = PTD1 and PTD0 configured for infrared LED drive capability; when a pin is set as an output, the pin is an open-drain pin with 25mA current sink capability 0 = PTD1 and PTD0 configured as standard I/O port pins
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Input/Output (I/O) Ports
PTE4P -- Pin PTE4 Pullup Enable This read/write bit controls the pullup option for the PTE4 pin when the pin is configured as an input and the USB module is disabled. 1 = Configure PTE4 to have internal pullup 0 = Disconnect PTE4 internal pullup
NOTE:
When the USB module is enabled, the pullup controlled by PTE4P is disconnected; PTE4/D- pin functions as D- which has a 1.5k programmable pull-up resistor. (See 11.8.8 USB Control Register 3.) PTE3P -- Pin PTE3 Pullup Enable This read/write bit controls the pullup option for the PTE3 pin when the pin is configured as an input and the USB module is disabled. 1 = Configure PTE3 to have internal pullup 0 = Disconnect PTE3 internal pullup PCP -- Port C Pullup Enable This read/write bit controls the pullup option for the PTC1 and PTC0 pins. When set, a pullup device is connected when a pin is configured as an input. 1 = Configure port C to have internal pullups 0 = Disconnect port C internal pullups PBP -- Port B Pullup Enable This read/write bit controls the pullup option for PTB0 pin. When set, a pullup device is connected when PTB0 is configured as an input. 1 = Disconnect PTB0 internal pullup 0 = Configure PTB0 to have internal pullup PAP -- Port A Pullup Enable This read/write bit controls the pullup option for the PTA7-PTA0 pins. When set, a pullup device is connected when a pin is configured as an input. 1 = Configure port A to have internal pullups 0 = Disconnect port A internal pullups
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Technical Data 274
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Technical Data -- MC68HC908JG16
Section 15. External Interrupt (IRQ)
15.1 Contents
15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 PTE4/D- Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .279 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 280 IRQ Option Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . 281
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15.3 15.4 15.5 15.6 15.7 15.8 15.9
15.2 Introduction
The IRQ module provides two external interrupt inputs: one dedicated IRQ pin and one shared port pin, PTE4/D-.
15.3 Features
Features of the IRQ module include: * * * * * * *
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Two external interrupt pins, IRQ and PTE4/D- IRQ interrupt control bits Hysteresis buffer Programmable edge-only or edge and level interrupt sensitivity Automatic interrupt acknowledge Low leakage IRQ pin for external RC wake up input Selectable internal pullup resistor
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External Interrupt (IRQ) 15.4 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 15-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: * Vector fetch -- A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch. Software clear -- Software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (ISCR). Writing a logic 1 to the ACK bit clears the IRQ latch. Reset -- A reset automatically clears the interrupt latch.
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*
*
The external interrupt pin is falling-edge-triggered and is softwareconfigurable to be either falling-edge or low-level-triggered. The MODE bit in the ISCR controls the triggering sensitivity of the IRQ pin. When the interrupt pin is edge-triggered only, the CPU interrupt request remains set until a vector fetch, software clear, or reset occurs. When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set until both of the following occur: * * Vector fetch or software clear Return of the interrupt pin to logic one
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK bit in the ISCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. (See 8.6 Exception Control.)
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External Interrupt (IRQ) Functional Description
INTERNAL ADDRESS BUS
ACK RESET VECTOR FETCH DECODER HIGH VOLTAGE DETECT TO MODE SELECT LOGIC TO CPU FOR BIL/BIH INSTRUCTIONS
VDD IRQPD "1"
INTERNAL
PULLUP DEVICE
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IRQF D CLR Q SYNCHRONIZER
IRQ
CK IRQ FF IMASK
IRQ INTERRUPT REQUEST
TO PTE4 PULLUP ENABLE CIRCUITRY
MODE
"1" D PTE4 CLR Q
READ IOCR PTE4IF
CK
PTE4IE
Figure 15-1. IRQ Module Block Diagram
Addr. $001C Register Name IRQ Option Control Register Read: (IOCR) Write: Reset: $001E IRQ Status and Control Register Read: (ISCR) Write: Reset: Bit 7 0 6 0 5 0 4 0 3 0 2 PTE4IF PTE4IE 0 0 0 0 0 0 0 0 0 IRQF 0 0 IMASK ACK 0 0 0 0 0 0 0 0 MODE 0 IRQPD 0 1 Bit 0
= Unimplemented
Figure 15-2. IRQ I/O Register Summary
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External Interrupt (IRQ) 15.5 IRQ Pin
The IRQ pin has a low leakage for input voltages ranging from 0V to VDD; suitable for applications using RC discharge circuitry to wake up the MCU. A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and lowlevel-sensitive. With MODE set, both of the following actions must occur to clear IRQ: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK bit in the interrupt status and control register (ISCR). The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at locations $FFF8 and $FFF9. Return of the IRQ pin to logic one -- As long as the IRQ pin is at logic zero, IRQ remains active.
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*
The vector fetch or software clear and the return of the IRQ pin to logic one may occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic zero. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the ISCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred.
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External Interrupt (IRQ) PTE4/D- Pin
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. An internal pullup resistor to VDD is connected to IRQ pin; this can be disabled by setting the IRQPD bit in the IRQ option control register ($001C).
15.6 PTE4/D- Pin
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The PTE4 pin is configured as an interrupt input to trigger the IRQ interrupt when the following conditions are satisfied: * * The USB module is disabled (USBEN = 0) PTE4 pin configured for external interrupt input (PTE4IE = 1)
Setting PTE4IE configures the PTE4 pin to an input pin with an internal pullup device. The PTE4 interrupt is "ORed" with the IRQ input to trigger the IRQ interrupt (see Figure 15-1 . IRQ Module Block Diagram). Therefore, the IRQ status and control register affects both the IRQ pin and the PTE4 pin. An interrupt on PTE4 also sets the PTE4 interrupt flag, PTE4IF, in the IRQ option control register (IOCR).
15.7 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. (See Section 8. System Integration Module (SIM).) To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latches during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch.
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External Interrupt (IRQ) 15.8 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR has the following functions: * * * * Shows the state of the IRQ flag Clears the IRQ latch Masks IRQ interrupt request Controls triggering sensitivity of the IRQ pin.
$001E Bit 7 Read: Write: Reset: 0 0 0 0 0 0 6 0 5 0 4 0 3 IRQF 2 0 IMASK ACK 0 0 0 MODE 1 Bit 0
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Address:
= Unimplemented
Figure 15-3. IRQ Status and Control Register (ISCR) IRQF -- IRQ Flag This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK -- IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always reads as logic 0. Reset clears ACK. IMASK -- IRQ Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE -- IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ pin interrupt requests on falling edges and low levels 0 = IRQ pin interrupt requests on falling edges only
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External Interrupt (IRQ) IRQ Option Control Register
15.9 IRQ Option Control Register
The IRQ option control register controls and monitors the external interrupt function available on the PTE4 pin. It also disables/enables the pullup resistor on the IRQ pin. * * * Controls pullup option on IRQ pin Enables PTE4 pin for external interrupts to IRQ Shows the state of the PTE4 interrupt flag
$001C Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 PTE4IF PTE4IE IRQPD 1 Bit 0
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Address:
= Unimplemented
Figure 15-4. IRQ Option Control Register (IOCR) PTE4IF -- PTE4 Interrupt Flag This read-only status bit is high when a falling edge on PTE4 pin is detected. PTE4IF bit clears when the IOCR is read. 1 = Falling edge on PTE4 is detected and PTE4IE is set 0 = Falling edge on PTE4 is not detected or PTE4IE is clear PTE4IE -- PTE4 Interrupt Enable This read/write bit enables or disables the interrupt function on the PTE4 pin to trigger the IRQ interrupt. Setting the PTE4IE bit and clearing the USBEN bit in the USB address register configure the PTE4 pin for interrupt function to the IRQ interrupt. Setting PTE4IE also enables the internal pullup on PTE4 pin. 1 = PTE4 interrupt enabled; triggers IRQ interrupt 0 = PTE4 interrupt disabled IRQPD -- IRQ Pullup Disable This read/write bit controls the pullup option for the IRQ pin. 1 = Internal pullup is disconnected 0 = Internal pull-up is connected between IRQ pin and VDD
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External Interrupt (IRQ)
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Technical Data 282 External Interrupt (IRQ) For More Information On This Product, Go to: www.freescale.com
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Technical Data -- MC68HC908JG16
Section 16. Keyboard Interrupt Module (KBI)
16.1 Contents
16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
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16.3 16.4 16.5 16.6
16.7 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16.7.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 288 16.7.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 289 16.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 16.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.9 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .290
16.2 Introduction
The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0-PTA7 pins.
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Keyboard Interrupt Module (KBI) 16.3 Features
Features of the keyboard interrupt module include: * * * * Eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask Hysteresis buffers Programmable edge-only or edge- and level-interrupt sensitivity Exit from low-power modes
Bit 7 0 6 0 5 0 4 0 3 KEYF 2 0 IMASKK ACKK 0 KBIE7 0 0 KBIE6 0 0 KBIE5 0 0 KBIE4 0 0 KBIE3 0 0 KBIE2 0 0 KBIE1 0 0 KBIE0 0 MODEK 1 Bit 0
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Addr.
Register Name
Read: Keyboard Status and Control $0016 Register Write: (KBSCR) Reset: Read: Keyboard Interrupt Enable Register Write: (KBIER) Reset:
$0017
= Unimplemented
Figure 16-1. I/O Register Summary
16.4 Pin Name Conventions
The KBI share eight I/O pins with eight port A I/O pins. The full name of the I/O pins are listed in Table 16-1. The generic pin name appear in the text that follows. Table 16-1. Pin Name Conventions
Full MCU Pin Name PTA7/KBA7-PTA0/KBA0 KBI Generic Pin Name KBA7-KBA0 Pin Selected for KBI Function by KBIEx Bit in KBIER KBIE7-KBIE0
Technical Data 284 Keyboard Interrupt Module (KBI) For More Information On This Product, Go to: www.freescale.com
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Keyboard Interrupt Module (KBI) Functional Description
16.5 Functional Description
INTERNAL BUS
KBA0 VREG . KBIE0 TO PULLUP ENABLE . . KBA7 D CLR Q
ACKK RESET
VECTOR FETCH DECODER KEYF SYNCHRONIZER Keyboard Interrupt Request
CK
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KEYBOARD INTERRUPT FF
IMASKK
MODEK KBIE7 TO PULLUP ENABLE
Figure 16-2. Keyboard Module Block Diagram Writing to the KBIE7-KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. * If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low.To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low.
*
If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request:
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Keyboard Interrupt Module (KBI)
* Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register (KBSCR). The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFE0 and $FFE1. Return of all enabled keyboard interrupt pins to logic 1 -- As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set.
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*
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edgesensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register.
NOTE:
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin.
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Keyboard Interrupt Module (KBI) Keyboard Initialization
16.6 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the pullup device to reach a logic 1. Therefore, a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register.
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2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in data direction register A. 2. Write logic 1s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
16.7 I/O Registers
These registers control and monitor operation of the keyboard module: * * Keyboard status and control register (KBSCR) Keyboard interrupt enable register (KBIER)
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Keyboard Interrupt Module (KBI)
16.7.1 Keyboard Status and Control Register * * * *
Address:
Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity
$0016 Bit 7 6 0 5 0 4 0 3 KEYF 2 0 IMASKK MODEK 0 ACKK 0 0 0 0 0 0 0 1 Bit 0
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Read: Write: Reset:
0
= Unimplemented
Figure 16-3. Keyboard Status and Control Register (KBSCR) KEYF -- Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK -- Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK -- Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK -- Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only
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Keyboard Interrupt Module (KBI) Low-Power Modes
16.7.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard interrupt pin.
Address: $0017 Bit 7 Read: KBIE7 Write: KBIE6 0 KBIE5 0 KBIE4 0 KBIE3 0 KBIE2 0 KBIE1 0 KBIE0 0 6 5 4 3 2 1 Bit 0
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Reset:
0
Figure 16-4. Keyboard Interrupt Enable Register (KBIER) KBIE7-KBIE0 -- Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = PTAx/KBAx pin enabled as keyboard interrupt pin 0 = PTAx/KBAx not enabled as keyboard interrupt pin
16.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
16.8.1 Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode.
16.8.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
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Keyboard Interrupt Module (KBI) 16.9 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state.
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To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. (See 16.7.1 Keyboard Status and Control Register.)
Technical Data 290 Keyboard Interrupt Module (KBI) For More Information On This Product, Go to: www.freescale.com
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Technical Data -- MC68HC908JG16
Section 17. Computer Operating Properly (COP)
17.1 Contents
17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
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17.3
17.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.1 OSCDCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 17.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 17.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 17.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 294 17.5 17.6 17.7 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
17.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 17.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 17.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 17.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .296
17.2 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register.
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Computer Operating Properly (COP) 17.3 Functional Description
Figure 17-1 shows the structure of the COP module.
OSCDCLK
12-BIT COP PRESCALER CLEAR ALL STAGES CLEAR STAGES 5-12
RESET CIRCUIT RESET STATUS REGISTER
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STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH COPCTL WRITE
COP CLOCK
6-BIT COP COUNTER COPEN (FROM SIM) COP DISABLE (COPD FROM CONFIG) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG)
CLEAR COP COUNTER
Figure 17-1. COP Block Diagram The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218 - 24 or 213 - 24 OSCDCLK cycles, depending on the state of the COP rate select bit, COPRS, in configuration register 1. With a 218 - 24 OSCDCLK cycle overflow option, a 24MHz OSCDCLK (12MHz crystal) gives a COP timeout period of 10.92ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the prescaler.
NOTE:
Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow.
Technical Data 292 Computer Operating Properly (COP) For More Information On This Product, Go to: www.freescale.com
COP TIMEOUT
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Computer Operating Properly (COP) I/O Signals
A COP reset pulls the RST pin low for 32 OSCDCLK cycles and sets the COP bit in the SIM reset status register (SRSR). In monitor mode, the COP is disabled if the RST pin or the IRQ is held at VTST. During the break state, VTST on the RST pin disables the COP.
NOTE:
Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.
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17.4 I/O Signals
The following paragraphs describe the signals shown in Figure 17-1.
17.4.1 OSCDCLK OSCDCLK is the crystal oscillator clock doubler output signal. Its frequency is two times the crystal frequency.
17.4.2 STOP Instruction The STOP instruction clears the COP prescaler.
17.4.3 COPCTL Write Writing any value to the COP control register (COPCTL) (see 17.5 COP Control Register) clears the COP counter and clears bits 12 through 5 of the prescaler. Reading the COP control register returns the low byte of the reset vector.
17.4.4 Power-On Reset The power-on reset (POR) circuit clears the COP prescaler 4096 OSCDCLK cycles after power-up.
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Computer Operating Properly (COP)
17.4.5 Internal Reset An internal reset clears the COP prescaler and the COP counter.
17.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler.
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17.4.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the CONFIG register. (See Figure 17-2.)
17.4.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the CONFIG register. (See Figure 17-2.)
Address: $001F Bit 7 Read: LVIDR Write: Reset: 0* 0* 0* 0* 0 0 0 0 LVI5OR3 URSTD LVID SSREC COPRS STOP COPD 6 5 4 3 2 1 Bit 0
* LVIDR, LVI5OR3, URSTD, and LVID, are reset by POR or LVI reset only.
Figure 17-2. Configuration Register (CONFIG) COPRS -- COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS. 1 = COP timeout period is 213 - 24 OSCDCLK cycles 0 = COP timeout period is 218 - 24 OSCDCLK cycles COPD -- COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled
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Computer Operating Properly (COP) COP Control Register
17.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: $FFFF Bit 7 6 5 4 3 2 1 Bit 0
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Read: Write: Reset:
Low byte of reset vector Clears COP counter (any value) Unaffected by reset
Figure 17-3. COP Control Register (COPCTL)
17.6 Interrupts
The COP does not generate CPU interrupt requests.
17.7 Monitor Mode
When monitor mode is entered with VTST on the IRQ pin, the COP is disabled as long as VTST remains on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not having VTST on the IRQ pin, the COP is automatically disabled until a POR occurs.
17.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
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Computer Operating Properly (COP)
17.8.1 Wait Mode The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine.
17.8.2 Stop Mode Stop mode turns off the OSCDCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction is disabled, execution of a STOP instruction results in an illegal opcode reset.
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17.9 COP Module During Break Mode
The COP is disabled during a break interrupt when VTST is present on the RST pin.
Technical Data 296 Computer Operating Properly (COP) For More Information On This Product, Go to: www.freescale.com
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Technical Data -- MC68HC908JG16
Section 18. Low-Voltage Inhibit (LVI)
18.1 Contents
18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
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18.3
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 18.4.1 Low VDD Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 18.4.2 Low VREG Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 18.5 LVI Control and Configuration . . . . . . . . . . . . . . . . . . . . . . . . 299
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
18.2 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and VREG pin. and can force a reset when the VDD or VREG voltage falls below the LVI trip falling voltage.
18.3 Features
Features of the LVI module include: * * * Independent voltage monitoring circuits for VDD and VREG Independent LVI circuit disable for VDD and VREG Selectable LVI trip voltage for VDD
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Low-Voltage Inhibit (LVI)
VDD
LVID
LOW VDD DETECTOR
VDD > VLVR = 0 VDD < VLVR = 1
LVI5OR3
LVI RESET
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VREG
LVIDR
LOW VREG DETECTOR
VDD > VLVRR = 0 VDD < VLVRR = 1
Figure 18-1. LVI Module Block Diagram
18.4 Functional Description
Figure 18-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module contains independent bandgap reference circuit and comparator for monitoring the VDD voltage and the VREG voltage. An LVI reset performs a MCU internal reset and drives the RST pin low to provide low-voltage protection to external peripheral devices.
18.4.1 Low VDD Detector The low VDD detector circuit monitors the VDD voltage and forces a LVI reset when the VDD voltage falls below the trip voltage. The LVI5OR3 bit in the configuration register (CONFIG) selects the trip point voltage. The VDD LVI circuit can be disabled by the setting the LVID bit in CONFIG. See 8.4.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI.
Technical Data 298 Low-Voltage Inhibit (LVI) For More Information On This Product, Go to: www.freescale.com
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Low-Voltage Inhibit (LVI) LVI Control and Configuration
18.4.2 Low VREG Detector The low VREG detector circuit monitors the VREG voltage and forces a LVI reset when the VREG voltage falls below the trip voltage. The VREG LVI circuit can be disabled by the setting the LVIDR bit in CONFIG.
NOTE:
There is no LVI circuit for VREGA.
18.5 LVI Control and Configuration
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Three bits in the configuration register (CONFIG) control the operation of the LVI module.
Address: $001F Bit 7 Read: LVIDR Write: Reset: 0* 0* 0* 0* 0 0 0 0 LVI5OR3 URSTD LVID SSREC COPRS STOP COPD 6 5 4 3 2 1 Bit 0
= Unimplemented * LVIDR, LVI5OR3, URSTD, and LVID bits are reset by POR (power-on reset) or LVI reset only.
Figure 18-2. Configuration Register (CONFIG) LVIDR -- LVI Disable Bit for VREG LVIDR disables the LVI circuit for VREG. 1 = LVI circuit for VREG disabled 0 = LVI circuit for VREG enabled LVI5OR3 -- LVI Trip Point Voltage Select Bit for VDD LVI5OR3 selects the trip point voltage of the LVI circuit for VDD. See Section 20. Electrical Specifications for the trip voltage tolerances. 1 = LVI trips at 3.3V 0 = LVI trips at 2.4V LVID -- LVI Disable Bit for VDD LVID disables the LVI circuit for VDD. 1 = LVI circuit for VDD disabled 0 = LVI circuit for VDD enabled
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Low-Voltage Inhibit (LVI) For More Information On This Product, Go to: www.freescale.com Technical Data 299
Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI) 18.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low powerconsumption standby modes.
18.6.1 Wait Mode If enabled, the LVI module remains active in wait mode.
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18.6.2 Stop Mode If enabled, the LVI module remains active in stop mode.
Technical Data 300 Low-Voltage Inhibit (LVI) For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
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Technical Data -- MC68HC908JG16
Section 19. Break Module (BRK)
19.1 Contents
19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
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19.3
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 19.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . .304 19.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 304 19.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 304 19.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 304 19.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 19.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 19.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 19.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 19.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . 305 19.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .306 19.6.3 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 308
19.2 Introduction
This section describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
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Technical Data 301
Freescale Semiconductor, Inc.
Break Module (BRK) 19.3 Features
Features of the break module include: * * * * Accessible input/output (I/O) registers during the break interrupt CPU-generated break interrupts Software-generated break interrupts COP disabling during break interrupts
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19.4 Functional Description
When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: * * A CPU-generated address (the address in the program counter) matches the contents of the break address registers. Software writes a logic 1 to the BRKA bit in the break status and control register.
When a CPU-generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 19-1 shows the structure of the break module.
Technical Data 302 Break Module (BRK) For More Information On This Product, Go to: www.freescale.com
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Break Module (BRK) Functional Description
IAB15-IAB8
BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB15-IAB0 CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW BREAK
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IAB7-IAB0
Figure 19-1. Break Module Block Diagram
Addr.
Register Name
Bit 7 R
6 R
5 R
4 R
3 R
2 R
1 SBSW Note 0
Bit 0 R
Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Read: SIM Break Flag Control Write: Register (SBFCR) Reset: Read: Break Address Register Write: High (BRKH) Reset: Read: Break Address Register Write: Low (BRKL) Reset:
$FE03
BCFE 0 Bit 15 0 Bit 7 0 BRKE 0
R
R
R
R
R
R
R
$FE0C
14 0 6 0 BRKA 0
13 0 5 0 0
12 0 4 0 0
11 0 3 0 0
10 0 2 0 0
9 0 1 0 0
Bit 8 0 Bit 0 0 0
$FE0D
Read: Break Status and Control $FE0E Write: Register (BRKSCR) Reset:
Note: Writing a logic 0 clears SBSW.
0
0
0 R
0 = Reserved
0
0
= Unimplemented
Figure 19-2. Break Module I/O Register Summary
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Break Module (BRK)
19.4.1 Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state.
19.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: * Loading the instruction register with the SWI instruction Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
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*
The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
19.4.3 TIM During Break Interrupts A break interrupt stops the timer counters.
19.4.4 COP During Break Interrupts The COP is disabled during a break interrupt when VTST is present on the RST pin.
19.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
19.5.1 Wait Mode If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if SBSW is set (see Section 8. System Integration Module (SIM)). Clear the SBSW bit by writing logic 0 to it.
Technical Data 304 Break Module (BRK) For More Information On This Product, Go to: www.freescale.com MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Break Module (BRK) Break Module Registers
19.5.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register.
19.6 Break Module Registers
These registers control and monitor operation of the break module:
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* * * * *
Break status and control register (BRKSCR) Break address register high (BRKH) Break address register low (BRKL) SIM break status register (SBSR) SIM break flag control register (SBFCR)
19.6.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits.
Address: $FE0E Bit 7 Read: BRKE Write: Reset: 0 0 0 0 0 0 0 0 BRKA 6 5 0 4 0 3 0 2 0 1 0 Bit 0 0
= Unimplemented
Figure 19-3. Break Status and Control Register (BRKSCR) BRKE -- Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match
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Technical Data 305
Freescale Semiconductor, Inc.
Break Module (BRK)
BRKA -- Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = (When read) Break address match 0 = (When read) No break address match
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19.6.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers.
Address: $FE0C Bit 7 Read: Bit 15 Write: Reset: 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0
Figure 19-4. Break Address Register High (BRKH)
Address: $FE0D Bit 7 Read: Bit 7 Write: Reset: 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0
Figure 19-5. Break Address Register Low (BRKL)
19.6.3 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt.
Technical Data 306 Break Module (BRK) For More Information On This Product, Go to: www.freescale.com
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Break Module (BRK) Break Module Registers
Address:
$FE00 Bit 7 6 R 5 R 4 R 3 R 2 R Note 0 R = Reserved 1 SBSW R R Bit 0
Read: Write: Reset:
Note: Writing a logic 0 clears SBSW.
Figure 19-6. SIM Break Status Register (SBSR)
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SBSW -- SIM Break Stop/Wait Bit This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break interrupt routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example.
; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the break ; service routine software. HIBYTE LOBYTE ; EQU EQU 5 6
If not SBSW, do RTI BRCLR TST BNE DEC DOLO RETURN DEC PULH RTI SBSW,SBSR, RETURN LOBYTE,SP DOLO HIBYTE,SP LOBYTE,SP ; See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ;Point to WAIT/STOP opcode. ;Restore H register.
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Technical Data 307
Freescale Semiconductor, Inc.
Break Module (BRK)
19.6.4 SIM Break Flag Control Register The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: $FE03 Bit 7 Read: BCFE Write: R R R R R R R 6 5 4 3 2 1 Bit 0
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Reset:
0 R = Reserved
Figure 19-7. SIM Break Flag Control Register (SBFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
Technical Data 308 Break Module (BRK) For More Information On This Product, Go to: www.freescale.com
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Technical Data -- MC68HC908JG16
Section 20. Electrical Specifications
20.1 Contents
20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .310 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 311 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 312 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 314
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20.3 20.4 20.5 20.6 20.7 20.8 20.9
20.10 USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 314 20.11 USB Low-Speed Source Electrical Characteristics . . . . . . . . 315 20.12 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 20.13 ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 317 20.14 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . 318
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Electrical Specifications 20.2 Introduction
This section contains electrical and timing specifications.
20.3 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it.
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NOTE:
This device is not guaranteed to operate properly at the maximum ratings. Refer to 20.6 DC Electrical Characteristics for guaranteed operating conditions.
Characteristic(1) Supply voltage Input voltage PTE4/D-, PTE3/D+ Others Mode entry voltage, IRQ pin Maximum current per pin excluding VDD and VSS Storage temperature Maximum current out of VSS /VSS Maximum current into VDD /VDDA
Notes: 1. Voltages referenced to VSS
Symbol VDD VIN
VTST
Value -0.3 to +6.0 VSS - 1.0 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 VSS -0.3 to +8 25 -55 to +150 100 100
Unit V V V mA C mA mA
I TSTG IMVSS IMVDD
NOTE:
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD).
Technical Data 310 Electrical Specifications For More Information On This Product, Go to: www.freescale.com
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Electrical Specifications Functional Operating Range
20.4 Functional Operating Range
Characteristic Operating temperature range Operating voltage range Symbol TA VDD Value 0 to 70 4.0 to 5.5 Unit C V
20.5 Thermal Characteristics
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Characteristic Thermal Resistance LQFP (32 pins) I/O pin power dissipation dissipation(1)
Symbol JA PI/O PD
Value 95 User-determined PD = (IDD x VDD) + (IDDA x VDDA) + PI/O = K/(TJ + 273 C) PD x (TA + 273 C) + PD2 x JA TA + (PD x JA) 100
Unit C/W W W
Power
Constant(2) Average junction temperature Maximum junction temperature
K TJ TJM
W/C C C
Notes: 1. Power dissipation is a function of temperature. 2. K is a constant unique to the device. K can be determined for a known TA and measure PD. With this value of K, PD and TJ can be determined for any value of TA.
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Electrical Specifications 20.6 DC Electrical Characteristics
Characteristic(1) Regulator output voltage Output high voltage (ILoad = -2.0 mA) PTA0-PTA7, PTB0, PTC0-PTC1, PTE0-PTE2 Output low voltage (ILoad = 1.6 mA) All I/O pins (ILoad = 25 mA) PTD0-PTD1 in ILDD mode (ILoad = 10 mA) PTE3-PTE4 with USB is disabled Input high voltage OSC1 All ports, IRQ, RST Input low voltage OSC1 All ports, IRQ, RST Output low current (VOL = 2.0 V) PTD2-PTD5 in LDD mode VDD supply current, VDD = 5.25V, fOP = 6MHz Run, with low speed USB(3) Run, with USB suspended(3) Wait, with low speed USB(4) Wait, with USB suspended(4) Stop (0 C to 70C)(5) I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) POR re-arm voltage(6) POR rise-time ramp rate(7) Monitor mode entry voltage Pullup resistors Port A, PTB0, port C, PTE0-PTE2, RST, IRQ (to VDD) PTE3-PTE4 with USB module disabled (to VDD) D- with USB module enabled (to VREG) VDD LVI trip point voltage (LVI5OR3 = 0) VDD LVI trip point voltage (LVI5OR3 = 1) VREG LVI trip point voltage Technical Data 312 Electrical Specifications For More Information On This Product, Go to: www.freescale.com VLVR -- -- -- -- -- -- -- -- -- 0 0.035 VDD + 2.5 20 4 1.1 2.0 2.8 2.0 35 5 1.5 2.4 3.3 2.2 7.0 6.5 3.0 2.5 60 -- -- -- -- -- -- 8.5 8.0 5.0 4.0 100 10 1 12 8 100 -- 8 50 6 2.0 2.8 3.8 2.6 V mA mA mA mA A A A pF mV V/ms V Symbol VREG VREGA VOH Min 3.0 2.9 VDD -0.8 Typ(2) 3.3 3.3 -- Max 3.6 3.7 -- Unit V V
VOL
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-- -- -- 0.7 x VREG 0.7 x VDD VSS VSS 10
-- -- -- -- -- -- -- 13
0.4 0.5 0.4 VREG VDD 0.3 x VREG 0.3 x VDD 20
V
VIH
V
VIL
V
IOL
mA
IDD
IIL IIN COut CIn VPOR RPOR VTST
RPU
k
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Electrical Specifications Control Timing
Notes: 1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source (fXCLK = 12MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fXCLK = 12MHz); all inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs. CL = 20 pF on OSC2; 15 k 5% termination resistors on D+ and D- pins; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD 5. STOP IDD measured with USB in suspend mode; OSC1 grounded; no port pins sourcing current. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached.
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20.7 Control Timing
Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min -- 125 Max 6 -- Unit MHz ns
Notes: 1. VDD = 4.0 to 5.5 Vdc; VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
20.8 Oscillator Characteristics
Characteristic Crystal frequency(1) External clock Reference frequency(1), (2) Crystal load capacitance(3) Crystal fixed capacitance(3) Crystal tuning capacitance(3) Feedback bias resistor Series resistor(3), (4) Symbol fXCLK fXCLK CL C1 C2 RB RS Min 1 dc -- -- -- -- -- Typ 12 12 -- 2 x CL 2 x CL 10 M -- Max 12 12 -- -- -- -- -- Unit MHz MHz
Notes: 1. The USB module is designed to operate with fXCLK = 12 MHz. 2. No more than 10% duty cycle deviation from 50%. 3. Consult crystal vendor data sheet. 4. Not required for high-frequency crystals.
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Electrical Specifications 20.9 TImer Interface Module Characteristics
Characteristic Input capture pulse width Input clock pulse width Symbol tTIH, tTIL tTCH, tTCL Min 1/fOP (1/fOP) + 5 Max -- -- Unit ns ns
20.10 USB DC Electrical Characteristics
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Characteristic(1) Hi-Z state data line leakage Voltage input high (driven) Voltage input high (floating) Voltage input low Differential input sensitivity Differential common mode range Static output low Static output high Output signal crossover voltage Regulator bypass capacitor Regulator bulk capacitor
Symbol ILO VIH VIHZ VIL VDI VCM VOL VOH VCRS
CREGBYPASS
Conditions 0 VMin -10 2.0 2.7
Typ
Max +10
Unit A V
3.6 0.8
V V V
|(D+) - (D-)| Includes VDI Range RL of 1.425 K to 3.6 V RL of 14.25 K to GND
0.2 0.8 2.5 0.3 2.8 1.3 -- 0.1 4.7 3.6 2.0
V V V V F F
CREGBULK
Notes: 1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
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Electrical Specifications USB Low-Speed Source Electrical Characteristics
20.11 USB Low-Speed Source Electrical Characteristics
Characteristic(1) Internal operating frequency Transition time(2) Rise time Fall time Symbol fOP Conditions -- Min -- Typ 6 Max -- Unit MHz
tR tF tRFM tDRATE
CL = 200 pF CL = 600 pF CL = 200 pF CL = 600 pF tR/tF 1.5 Mbs 1.5% CL = 600 pF Measured at crossover point CL = 600 pF Measured at crossover point Measured at crossover point Measured at crossover point
75 75
-- 300 -- 300 ns
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Rise/Fall time matching Low speed data rate Source differential driver jitter To next transition For paired transitions Receiver data jitter tolerance To next transition For paired transitions Source SEO interval of EOP Source jitter for differential transition to SE0 transition(3) Receiver SEO interval of EOP Must reject as EOP Must accept Width of SEO interval during differential transition
80 1.4775 676.8 -25 -10
-- 1.500 666.0 -- --
120 1.5225 656.8 25 10
% Mbs ns ns
tDDJ1 tDDJ2 tDJR1 tDJR2 tLEOPT
-75 -45 1.25
-- -- -- 667
75 45 1.50
ns
s ns
tLEOPR1 tLEOPR2 tLST
Measured at crossover point Measured at crossover point
210 670 --
-- -- --
-- -- 210
ns
ns
Notes: 1. All voltages are measured from local ground, unless otherwise specified. All timings use a capacitive load of 50 pF, unless otherwise specified. Low-speed timings have a 1.5k pullup to 2.8 V on the D- data line. 2. Transition times are measured from 10% to 90% of the data signal. The rising and falling edges should be smoothly transitioning (monotonic). Capacitive loading includes 50 pF of tester capacitance. 3. The two transitions are a (nominal) bit time apart.
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Electrical Specifications 20.12 USB Signaling Levels
Signaling Levels Bus State Transmit Differential 1 Differential 0 Single-ended 0 (SE0) D+ > VOH (min) and D- < VOL (max) D- > VOH (min) and D- < VOL (max) D+ and D- < VOL (max) Differential 0 Differential 1 NA Differential 1 Data lines switch from Idle to K State SE0 for approximately 2 bit times(1) followed by a J state for 1 bit time NA SE0 for 1 bit time(2) followed by a J state for 1 bit time D+ and D- < VIL (max) for 8s Receive (D+) - (D-) > 200 mV (D-) - (D+) > 200 mV D+ and D- < VIL (max) Differential 0 Differential 1 D- > VIHZ (min) and D+ < VIL (max) Differential 1
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Data J state (low speed) Data K state (low speed) Idle state (low speed) Resume state Start of packet (SOP) End of packet (EOP) Reset
Notes: 1. The width of EOP is defined in bit times relative to the speed of transmission. 2. The width of EOP is defined in bit times relative to the device type receiving the EOP. The bit time is approximate.
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Electrical Specifications ADC Electrical Characteristics
20.13 ADC Electrical Characteristics
Characteristic(1) Symbol Min Max Unit Comments VDDA should be tied to the same potential as VDD via separate traces.
Supply voltage
VDDA
4.0
5.5
V
ADC reference voltage high ADC reference voltage low
VREFH VREFL VADIN BAD AAD fADIC RAD tADPU tADC tADS ZADI FADI CADI --
-- VSSA VREFL 8 -- 0.75 VREFL 16 16 5 00 FE -- --
VREGA -- VREFH 8 1 1.572 VREFH -- 17 -- 01 FF 8 1
V V V Bits LSB MHz V tAIC cycles tAIC cycles tAIC cycles HEX HEX pF A Not tested Includes quantization tAIC = 1/fADIC, tested only at 1.5 MHz
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Input voltages Resolution Absolute accuracy ADC internal clock Conversion range Power-up time Conversion time Sample time(2) Zero input reading(3) Full-scale reading(3) Input capacitance Input leakage(4) Port A
Notes: 1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Source impedances greater than 10 k adversely affect internal RC charging time during input sampling. 3. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 4. The external system error caused by input leakage current is approximately equal to the product of R source and input current.
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Electrical Specifications 20.14 FLASH Memory Characteristics
Characteristic RAM data retention voltage FLASH block size FLASH programming size FLASH read bus clock frequency FLASH block erase time Symbol VRDR -- -- fRead(1) tErase(2) tMErase(3) tnvs tnvh tnvhl tpgs tProg trcv(4) tHV(5) -- -- -- 32 k 10 200 5 5 100 10 20 1 -- 10k 10k 10 Min 1.3 512 64 8.4 M -- -- -- -- -- -- 40 -- 8 -- -- -- Max -- Unit V Bytes Bytes Hz ms ms s s s s s s ms Cycles Cycles Years
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FLASH mass erase time FLASH PGM/ERASE to HVEN set up time FLASH high-voltage hold time FLASH high-voltage hold time (mass erase) FLASH program hold time FLASH program time FLASH return to read time FLASH cumulative program hv period FLASH row erase endurance(6) FLASH row program endurance(7) FLASH data retention time(8)
Notes: 1. fRead is defined as the frequency range for which the FLASH memory can be read. 2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduced the endurance of the FLASH memory. 3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH memory. 4. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to logic 0. 5. tHV is defined as the cumulative high voltage programming time to the same row before next erase. 6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase / program cycles. 7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase / program cycles. 8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified.
Technical Data 318 Electrical Specifications For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Technical Data -- MC68HC908JG16
Section 21. Mechanical Specifications
21.1 Contents
21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 32-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . 320
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21.3
21.2 Introduction
This section gives the dimensions for: * 32-pin low-profile quad flat pack (case #873A)
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Mechanical Specifications For More Information On This Product, Go to: www.freescale.com
Technical Data 319
Freescale Semiconductor, Inc.
Mechanical Specifications 21.3 32-Pin Low-Profile Quad Flat Pack (LQFP)
-T-, -U-, -Z- AE P B1 DETAIL Y
8 17
A A1
32 25
4X
0.20 (0.008) AB T-U Z
1
-T- B
-U- V V1 AE
9
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DETAIL Y -Z-
4X
9
S1 S
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
F
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
Figure 21-1. 32-Pin LQFP (Case #873A)
Technical Data 320 Mechanical Specifications For More Information On This Product, Go to: www.freescale.com
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
EE EE EE EE
J
N
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Technical Data -- MC68HC908JG16
Section 22. Ordering Information
22.1 Contents
22.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
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22.3
22.2 Introduction
This section contains ordering numbers for the MC68HC908JG16.
22.3 MC Order Numbers
Table 22-1. MC Order Numbers
MC Order Number
MC68HC908JG16FA
Package
32-pin LQFP
Operating Temperature Range 0 to +70 C
MC68HC908JG16 -- Rev. 1.0 MOTOROLA Ordering Information For More Information On This Product, Go to: www.freescale.com
Technical Data 321
Freescale Semiconductor, Inc.
Ordering Information
Freescale Semiconductor, Inc...
Technical Data 322 Ordering Information For More Information On This Product, Go to: www.freescale.com
MC68HC908JG16 -- Rev. 1.0 MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
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